This appendix provides information on setting up the Synopsys interface and associated libraries. Example files are included to help you set up the FPGA Compiler and VSS with the Xilinx software. This chapter contains the following sections.
The following documentation is available for the Synopsys interface.
In addition to the environment variables described in the “Installing the Software” chapter, the following environment variables must be modified or added to run the Synopsys interface tools.
Set these variables as follows.
setenv SYNOPSYS installation_path_to_synopsys
set path = ($XILINX/bin/platform_name \
$SYNOPSYS/platform_name/syn/bin \
$SYNOPSYS/platform_name/sim/bin \
$path)
For Solaris only.
setenv LD_LIBRARY_PATH $SYNOPSYS/platform_name/sim/lib:$LD_LIBRARY_PATH
For HP/UX only.
setenv SHLIB_PATH $SYNOPSYS/platform_name/sim/lib:$SHLIB_PATH
The following is an example.
setenv SYNOPSYS /usr/synopsys
set path = ($XILINX/bin/sol \
$SYNOPSYS/sol/syn/bin \
$SYNOPSYS/sol/sim/bin \
$path)
setenv LD_LIBRARY_PATH $SYNOPSYS/sol/sim/lib:$LD_LIBRARY_PATH
If you are not using FPGA Compiler v1997.01or a later version, you must re-compile the Xilinx DesignWare (XDW) libraries.
The XSI (Xilinx Synopsys Interface) simulation and XDW (Xilinx DesignWare) libraries are compiled for Synopsys v1997.01. If you are using the latest version of XSI with a version of Synopsys newer than v1997.01, you must re-compile the XDW libraries with the version of Synopsys you are using. If you are going to simulate with VSS, you must re-compile the simulation libraries.
You can compile the libraries in the $XILINX area, or in some other area. If you compile the libraries in the $XILINX area, you must have write permissions to this area. If you copy the $XILINX/synopsys directory to a local area, you can re-compile the libraries without needing write permissions for the $XILINX area. However, verify that the .synopsys_dc.setup and .synopsys_vss.setup files use the local copy.
Follow these steps to compile the XDW libraries.
The following procedure is for compiling the XSI simulation libraries with VSS. If you are using a different HDL simulator, refer to your simulator's documentation for instructions on compiling HDL simulation libraries.
The “XSI Design Flow” figure shows the steps in the XSI design flow.
For more information on the XSI design flow, see the Synopsys (XSI) Interface/Tutorial Guide.
The following are inputs to the Design Compiler and the FPGA Compiler.
The following are outputs from the compilers.
Figure D.1 XSI Design Flow |  |
This section includes examples of the Synopsys setup files needed to run the FPGA Compiler and VSS with the Xilinx tools. These examples are for XC4000XL and Virtex devices. Other FPGA and CPLD templates are in the Xilinx installation path, $XILINX/synopsys/examples.
Although the following .synopsys_dc.setup file example is for an XC4000XL device, it is similar to the setup file required for XC4000E/EX/XLA/XV devices.
/* Template .synopsys_dc.setup file for Xilinx */
/* For targeting a XC4000XL */
XilinxInstall = get_unix_variable(XILINX);
SynopsysInstall = get_unix_variable(SYNOPSYS);
search_path = { . \
XilinxInstall + /synopsys/libraries/syn \
SynopsysInstall + /libraries/syn }
/* Define a work library.You must create `work' */
define_design_lib WORK -path ./WORK
/* Declare the Xilinx DesignWare library */
define_design_lib xdw_4000xl -path \
XilinxInstall + /synopsys/libraries/dw/lib/xc4000xl
/* General configuration settings. */
compile_fix_multiple_port_nets = true
xnfout_constraints_per_endpoint = 0
xnfout_library_version = "2.0.0"
bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
bus_inference_style = "%s<%d>"
/* synlibs -fc 4028ex-3 >> .synopsys_dc.setup *//* Set any simulation preferences. */
TIMEBASE = NS
TIME_RES_FACTOR = 0.1
/* Define a work library in the current project */
WORK > DEFAULT
DEFAULT : ./WORK
/* Set up SIMPRIM Back-annotation libraries */
SIMPRIM : $XILINX/synopsys/libraries/sim/lib/simprims
/* Set up LogiBLOX simulation libraries */
LOGIBLOX : $XILINX/synopsys/libraries/sim/lib/logiblox
/* Set up example pointers to the Xilinx Unisim functional simulation library */
UNISIM: $XILINX/synopsys/libraries/sim/lib/unisimsThis section describes the typical sequence of commands used to process designs with the Synopsys interface. You should run the commands at the dc_shell command line, either individually or in batch mode. While every design may not require all the commands used in this section, the following example represents a good starting point for most designs. This script file includes information on I/O pin location constraints, timing constraints, setting the part-type, controlling I/O characteristics, and controlling Synopsys mapping and packing functions.
/* Sample Script for Synopsys to Xilinx Using */
/* FPGA Compiler targeting a XC4000EX device*/
/* Set the name of the design's top-level */
TOP = <design_name>
designer = “XSI Team”
company = “Xilinx, Inc”
part = “4028expg299-3”
/* Analyze and Elaborate the design file. */
analyze -format vhdl TOP + “.vhd”
elaborate TOP
/* Set the current design to the top level. */
current_design TOP
/* Set the synthesis design constraints. */
remove_constraint -all
/* Some example constraints */
create_clock <clock_port_name> -period 50
set_input_delay 5 -clock <clock_port_name> \
{ <a_list_of_input_ports> }
set_output_delay 5 -clock <clock_port_name> \
{ <a_list_of_output_ports> }
set_max_delay 100 -from <source> -to <destination>
set_false_path -from <source> -to <destination>
/* Indicate which ports are pads. */
set_port_is_pad “*”
/* Some example I/O parameters */
set_pad_type -pullup <port_name>
set_pad_type -no_clock all_inputs()
set_pad_type -clock <clock_port_name>
set_pad_type -exact BUFGS_F <hi_fanout_port_name>
set_pad_type -slewrate HIGH all_outputs()
insert_pads
/* Synthesize the design.*/
compile -boundary_optimization -map_effort med
/* Write the design report files. */
report_fpga > TOP + ".fpga"
report_timing > TOP + ".timing"
/* Write out an intermediate DB file to save state*/
write -format db -hierarchy -output TOP + "_compiled .db"
/* Replace CLBs and IOBs primitives (XC4000E/EX/XL only)*/
replace_fpga
/* reapply set_max_delay/set_false_path if using FPGA compiler */
/* Set the part type for the output netlist.
set_attribute TOP "part" -type string part
/* Optional attribute to remove the mapping symbols*/set_attribute find(design,"*")\
"xnfout_write_map_ symbols" -type boolean FALSE
/* Add any I/O constraints to the design. */
set_attribute <port_name> "pad_location" \
-type string "<pad_location>"
/* Write out the intermediate DB file to save state*/
write -format db -hierarchy -output TOP + ".db"
/* Write out the timing constraints*/
ungroup -all -flatter
write_script > TOP + ".dc"
/* Save design in XNF format as <design>.sxnf */
write -format xnf -hierarchy -output TOP + ".sxnf"
/* Convert constraints to Xilinx syntax */
sh dc2ncf TOP + ".dc"
/* Exit the Compiler. */
exit/* Now run the Xilinx design implementation tools. */The following setup file examples are for Virtex devices.
/* =================================================== */
/* Template .synopsys_dc.setup file for Xilinx designs */
/* For use with Synopsys FPGA Compiler. */
/* =================================================== */
/* ================================================= */
/* The Synopsys search path should be set to point */
/* to the directories that contain the various */
/* synthesis libraries used by FPGA Compiler during */
/* synthesis. */
/* ================================================= */
XilinxInstall = get_unix_variable(XILINX);
SynopsysInstall = get_unix_variable(SYNOPSYS);
search_path = { . \
XilinxInstall + /synopsys/libraries/syn \
SynopsysInstall + /libraries/syn }
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
/* Ensure that your UNIX environment */
/* includes the two environment var- */
/* iables: $XILINX (points to the */
/* Xilinx installation directory) and*/
/* $SYNOPSYS (points to the Synopsys */
/* installation directory.) */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
/* ================================================= */
/* Define a work library in the current project dir */
/* to hold temporary files and keep the project area */
/* uncluttered. Note: You must create a subdirectory */
/* in your project directory called WORK. */
/* ================================================= */
define_design_lib WORK -path ./WORK
bus_extraction_style = "%s<%d:%d>"
bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
edifin_lib_logic_1_symbol = "VCC"
edifin_lib_logic_0_symbol = "GND"
edifout_ground_name = "GND"
edifout_ground_pin_name = "G"
edifout_power_name = "VCC"
edifout_power_pin_name = "P"
edifout_netlist_only = "true"
edifout_no_array = "false"
edifout_power_and_ground_representation = "cell"
edifout_write_properties_list = {"CLK1X_DUTY" "INIT_00" "INIT_01" "INIT_02" "INIT_03" \
"INIT_04" "INIT_05" "INIT_06" "INIT_07" "INIT_08" "INIT_09" "INIT_0A" "INIT_0B" "INIT_0C" \
"INIT_0D" "INIT_0E" "INIT_0F" "INIT" "CLKDV_DIVIDE" "IOB" "EQN" "lut_function"}
/* ================================================= */
/* Set the link, target and synthetic library */
/* variables. Use synlibs to */
/* determine the link and target library settings. */
/* You may like to copy this file to your project */
/* directory, rename it ".synopsys_dc.setup" and */
/* append the output of synlibs. For example: */
/* synlibs xfpga_virtex-3 >> .synopsys_dc.setup */
/* ================================================= */
link_library = {xfpga_virtex-5.db }
link_library = {xfpga_virtex-5.db }
symbol_library = {virtex.sdb}
define_design_lib xdw_virtex -path XilinxInstall + /synopsys/libraries/dw/lib/virtex
synthetic_library = {xdw_virtex.sldb standard.sldb}/* ================================================== */
/* Sample Script for Synopsys to Xilinx Using */
/* FPGA Compiler */
/* */
/* Targets the Xilinx XCV150PQ240-3 and assumes a */
/* VHDL source file by way of an example. */
/* */
/* For general use with VIRTEX architectures. */
/* ================================================== */
/* ================================================= */
/* Set the name of the design's top-level module. */
/* (Makes the script more readable and portable.) */
/* Also set some useful variables to record the */
/* designer and company name. */
/* ================================================= */
TOP = <design_name>
/* ========================== */
/* Note: Assumes design file- */
/* name and entity name are */
/* the same (minus extension) */
/* ========================== */
designer = "XSI Team"
company = "Xilinx, Inc"
part = "XCV150PQ240-3"
/* ================================================= */
/* Analyze and Elaborate the design file and specify */
/* the design file format. */
/* ================================================= */
analyze -format vhdl TOP + ".vhd"
/* ============================ */
/* You must analyze lower-level */
/* hierarchy modules here */
/* ============================ */
elaborate TOP
/* ================================================= */
/* Set the current design to the top level. */
/* ================================================= */
current_design TOP
/* ================================================= */
/* Set the synthesis design constraints. */
/* ================================================= */
remove_constraint -all
/* If setting timing constraints, do it here.
For example: */
/*
create_clock <clock_pad_name> -period 50
*/
/* ================================================= */
/* Indicate those ports on the top-level module that */
/* should become chip-level I/O pads. Assign any I/O */
/* attributes or parameters and perform the I/O */
/* synthesis. */
/* ================================================= */
set_port_is_pad "*"
set_pad_type -slewrate HIGH all_outputs()
insert_pads
/* +++++++++++++++++++++++++++++++++++++++++++++++++ */
/* Compile the design */
/* +++++++++++++++++++++++++++++++++++++++++++++++++ */
compile -map_effort med
/* ================================================= */
/* Write the design report files. */
/* ================================================= */
report_fpga > TOP + ".fpga"
report_timing > TOP + ".timing"
/* ================================================= */
/* Set the part type for the output netlist. */
/* ================================================= */
set_attribute TOP "part" -type string part
/* ================================================= */
/* Save design in EDIF format as <design>.sedif */
/* ================================================= */
write -format xnf -hierarchy -output TOP + ".sedif"
/* ==========
Timing constraints issued to Synopsys to control the synthesis process can be carried forward to the design implementation tools to control the place and route process. It is important that the constraints you apply to both the synthesis and place and route processes are both realistic and achievable.
The Xilinx DC2NCF utility converts the timing constraints applied to your design in the Synopsys environment to equivalent constraints that control the Xilinx place and route process. The automatic translation of these constraints is convenient because you do not need to apply the constraints twice. In addition, it ensures that the constraints used by the Xilinx tools are equivalent to those applied in Synopsys.
DC2NCF supports translation of the following timing constraints.
If there are unsupported timing constraints in the Synopsys script file, DC2NCF issues a warning message and the constraints are not translated.
You should validate your design timing constraints by first constraining your design and then compiling it. After compiling your design (for XC4000E/EX/XL/XV/XLA FPGA designs, you must also run the replace_fpga command), write your design as a netlist and a corresponding script file that contains the constraints.
WARNINGAlways generate timing constraints script files with the Synopsys dc_shell write_script command or the Design Analyzer File, Save Info, Design Setup command sequence.
Before writing either the netlist or the constraints file, any hierarchy in your XC4000E/EX/XL/XV/XLA designs must be flattened. Flattening your design removes hierarchy information from the Synopsys internal database. The hierarchical net-names and instance-names assigned to objects during compilation are retained and written into the output netlist.
The downstream Xilinx tools will reconstruct most of the design's hierarchy from the information carried in the instance-names and net-names.
To flatten the design's hierarchy prior to writing a netlist and constraints file, use the following Synopsys command.
Do not use the following command for Virtex designs.
ungroup -flatten -all
To write-out the design's netlist in XNF format, use the Synopsys command.
write -format xnf -output output_file_name.sxnf
To write-out the design's constraints as a Synopsys script file, use the command.
write_script > output_file_name.dc
This section includes VHDL and Verilog code examples.
library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_ARITH.all;use IEEE.STD_LOGIC_UNSIGNED.all;entity example isport(RAMOUT:out STD_LOGIC; DIN: in STD_LOGIC;AD4,AD3,AD2,AD1,AD0,RMWE,RMWCLK: in STD_LOGIC;REG1OUT: out STD_LOGIC; DTA1,CLK1: in STD_LOGIC;REG2OUT: out STD_LOGIC; DTA2,CLK2: in STD_LOGIC;LTCHOUT: out STD_LOGIC;LTD,LTGF,LTGE,LTCLK: in STD_LOGIC;FASTOUT: out STD_LOGIC; FASTIN: in STD_LOGIC;MUXOUT: out STD_LOGIC; MUXIN1,MUXIN2: in STD_LOGIC);end example;architecture inside of example issignal ground: STD_LOGIC;component RAM32X1Sport(O: out STD_LOGIC; D: in STD_LOGIC;A4,A3,A2,A1,A0,WE,WCLK: in STD_LOGIC);signal rstsig: STD_LOGIC;end component;component IFD_Fport(Q: out STD_LOGIC; D,C: in STD_LOGIC);end component;component OFD_Fport(Q: out STD_LOGIC; D,C: in STD_LOGIC);end component;component STARTBUFport(GSRIN: in STD_LOGIC; (GSTIN: in STD_LOGIC; (CLKIN: in STD_LOGIC; (GSROUT: out STD_LOGIC;D,GF,CE,C: in STD_LOGIC);end component;component BUFFCLKport(O: out STD_LOGIC; I: in STD_LOGIC);end component;component OAND2port(O: out STD_LOGIC; F,I0: in STD_LOGIC);end component;beginU0: RAM32X1S port map(O=>RAMOUT,D=>DIN,A4=>AD4,A3=>AD3,A2=>AD2,A1=>AD1,A0=>AD0,WE=>RMWE,WCLK=>RMWCLK);U1: IFD_F port map(Q=>REG1OUT,D=>DTA1,C=>CLK1);U2: OFD_F port map(Q=>REG2OUT,D=>DTA2,C=>CLK2);U3: STARTBUF port map (GSRIN=>RESET,GTSIN=>GROUND,CLKIN=>GROUND,GSROUT=>RSTSIG);U4: BUFFCLK port map(O=>FASTOUT,I=>FASTIN);U5: OAND2 port map(O=>MUXOUT,F=>MUXIN1,I0=>MUXIN2);end inside;module example ( RAMOUT,DIN,AD,RMWE,RMWCLK,
REG1OUT,DTA1,CLK1,REG2OUT,DTA2,CLK2,
LTCHOUT,LTD,LTGF,LTGE,LTCLK,
FASTOUT,FASTIN,MUXOUT,MUXIN1,MUXIN2);input RMWE,RMWCLK,DIN,DTA1,CLK1,DTA2,CLK2,LTD,LTGF,LTGE,LTCLKinput FASTIN,MUXIN1,MUXIN2;input [4:0] AD;output RAMOUT,REG1OUT,REG2OUT,LTCHOUT,FASTOUT,MUXOUT;RAM32X1S U0 (.O(RAMOUT),.D(DIN),.A4(AD[4]),.A3(AD[3]),.A2(AD[2]),.A1(AD[1]),.A0(AD[0]),.WE(RMWE),.WCLK(RMWCLK));IFD_F U1 (.Q(REG1OUT),.D(DTA1),.C(CLK1));OFD_F U2 (.Q(REG2OUT),.D(DTA2),.C(CLK2));BUFFCLK U4 (.O(FASTOUT),.I(FASTIN));OAND2 U5 (.O(MUXOUT),.F(MUXIN1),.I0(MUXIN2));endmoduleWhen instantiating IOB components such as IFD_F, OFD_F, ILFFX, BUFFCLK, or OAND2, make sure that unnecessary IBUF/OBUF/OBUFTs are not inserted. Remove the port_is_pad attribute from the pin that is directly connected to a pad, such as the D pin of the IFD_F, or the .D pin of the ILFFX. To remove the port_is_pad attributes, use the remove_attribute command.
For information on using LogiBLOX in the XSI flow, refer to the Synopsys (XSI) Interface/Tutorial Guide.
