Design Flows

The Foundation Series design tools interface supports two basic flows within the Project Manager: HDL and Schematic.

HDL Flow

The HDL Flow supports the following design strategies.

• All-VHDL or all-Verilog design with underlying LogiBLOXs, schematics (EDIF files), ABEL modules, and XNF files that are instantiated in the VHDL and Verilog code as “black boxes.” Black box modules are not elaborated and optimized during synthesis. State machine modules are synthesized as VHDL or Verilog.
  
  
• Mixed-HDL (VHDL and Verilog) designs with underlying LogiBLOXs, schematics (EDIF files), ABEL modules, and XNF files that are instantiated in the VHDL and Verilog code as “black boxes.” State machine modules are synthesized as VHDL or Verilog.
  
  

For a detailed description of the design methodologies, refer to the “Design Methodologies - HDL Flow” chapter in the Foundation Series User Guide.

Schematic Flow

The Schematic Flow supports the following design strategies.

• Top-level schematic design with the Xilinx Unified Libraries components, LogiBLOX symbols, and ABEL, HDL and/or state machine macros
  
  
• Top-level ABEL-based designs (not recommended for FPGA designs)
  
  
• Top-level State Machine designs
  
  

For a detailed description of the design methodologies, refer to the “Design Methodologies - Schematic Flow” chapter in the Foundation Series User Guide.

NOTE

Foundation Express supports designs having top-level HDL descriptions (either VHDL or Verilog). See the “In-Depth Tutorial - HDL-Based Design” chapter in this manual.
Also refer to the “HDL Design Entry and Synthesis” chapter in the Foundation Series User Guide.

The following two figures illustrate the basic design flow for FPGAs and CPLDs. For detailed design flow illustrations, refer to the “File Processing Overview” appendix in the Foundation Series User Guide.

Figure 3.1 Foundation Overall Design Flow for FPGAs

Figure 3.2 Foundation Overall Design Flow for CPLDs