Chapter 3

Foundation Overview

This overview explains the basic concepts and design flow of the Foundation Series 1.5 release as it spans the flow from netlist to final PROM file. This chapter contains the following sections:

• “Design Flows”
  
  
• “Using the Foundation Design Entry Tools”
  
  
• “Using the Design Implementation Tools”
  
  
• “Using Constraint Files”
  
  
• “Static Timing Analysis”
  
  
• “Creating Simulation Files”
  
  
• “Downloading a Design”
  
  
• “Re-Entrant Routing”
  
  

The flow described in this chapter is generally applicable to all Xilinx families. However, many of the details apply only to the FPGA device families. For complete information on CPLD design flows, refer to the Foundation online help.