Using the Foundation Design Entry Tools

This section describes the basic procedure for using the design entry tools.

Starting the Foundation Project Manager

To start the Project Manager, double click on the Project Manager icon in the Foundation Series program group. The icon to click is shown in the following figure.

The Foundation design tools environment (the Project Manager) is shown in the following figure.

Figure 3.3 Foundation Project Manager

A dialog box displays, asking if you want to open an existing project or create a new one.

To create a new project, follow these steps:

1. Open the Foundation Project Manager.
   
   
2. Select Create a New Project from the Getting Started dialog box. Click OK. Alternatively, select File Open Project or select the toolbar button.
   
   
   
   
3. After the New Project dialog box displays, enter a name for the project. Change the directory for the project, if desired, by using the Browse button.
   
   
4. Choose the appropriate family, part, and speed grade.
   
   
5. Click OK.
   
   

For more information about creating new projects in Foundation, refer to Foundation's online help system. For detailed information about the Project Manager, refer to the online help by selecting Help Foundation Help Contents Project Manager. Also see the “Project Manager” section of the “Project Toolset” chapter in the Foundation Series User Guide.

Creating Top-Level Schematic Designs

You can create a variety of top-level designs.

• All schematic designs
  
  
• Schematic designs with instantiated HDL macros
  
  
• Schematic designs with instantiated LogiBLOX modules
  
  
• Schematic designs with instantiated state machine macros
  
  
• Top-level ABEL-based designs
  
  
• State Machine designs
  
  

For a detailed description of the procedures for creating these types of designs, refer to the “In-Depth Tutorial - Schematic-Based Design” chapter.

Also refer to the “Design Methodologies - Schematic Flow” chapter in the Foundation Series User Guide.

For a discussion of schematic design issues, refer to the “Schematic Design Entry” chapter in the Foundation Series User Guide.

Creating Top-level VHDL/Verilog Designs

You can create VHDL and Verilog designs if you purchased a version of Foundation that includes the Synopsys FPGA Express package. FPGA Express is included with these Foundation versions: 1) Base Express, and 2) Foundation Express.

You can create a variety of top-level schematic VHDL or Verilog designs.

• All-HDL designs
  
  
• HDL designs with State Machine macros
  
  
• HDL designs with instantiated Xilinx Unified Library components
  
  
• HDL designs with black box instantiations
  
  

Black boxes are not synthesized by Express; they are passed to the implementation tools for translation by the Flow Engine.

For a detailed description of the procedures for creating these types of designs, refer to the “Design Methodologies - HDL Flow” chapter in the Foundation Series User Guide.

Also refer to the “In-Depth Tutorial - HDL-Based Design” chapter in this manual (the Quick Start Guide).

For a discussion of HDL design issues, refer to the “HDL Design Entry and Synthesis” chapter in the Foundation Series User Guide.

If you purchased FPGA Express (Base Express or Foundation Express), you use this software to synthesize your VHDL and Verilog designs. For information on how to use the VHDL and Verilog languages, refer to the online DynaText documents, VHDL Reference Guide and Verilog Reference Guide.

If you have a VHDL design from a previous release, which used the XVHDL compiler, you may continue to use the XVHDL compiler in F1.5. However, make sure that the Project Type is set to XACTstep M1 (File Project Type). The previous HDL synthesis tool cannot be used to create new designs.

Creating State Machine Designs

State machine designs typically start with the translation of a concept into a “paper design,” usually in the form of a state diagram or a bubble diagram. The paper design is converted to a state table and then, into the source code itself.

A State Machine design can be used in the following ways.

• Top-level design in a Schematic Flow
  
  
• A module in a schematic
  
  
• A module in a VHDL or Verilog design
  
  

For a detailed discussion of the design steps, refer to the “Design Methodologies - Schematic Flow” chapter and the “Design Methodologies - HDL Flow” chapter in the Foundation Series User Guide.

For a description of a sample state machine, refer to the “State Machine Designs” chapter in the Foundation Series User Guide.