Creating Simulation Files

After the design is implemented, you can perform a timing simulation to ascertain if the timing requirements and functionality of your design have been met. Timing simulation can save considerable time by reducing the time spent debugging test boards in the lab. Functional simulation can also potentially save time by uncovering design bugs before running PAR.

When Can Simulation Data be Created?

With the design implementation tools, you can create simulation data after each major processing step. This means that you can create functional simulation netlists 1) after the design has been merged together by NGDBuild in the Translate process, and 2) timing simulation netlists, after the design has been placed and routed by PAR for FPGAs or fitted by the CPLD fitter for CPLDs.

For FPGAs, simulation data created after the design has only been mapped contains timing data based on the CLB and IOB block delays, and all net (interconnect) delays are set to zero.

With post-map simulation, you can ensure that the design's current implementation will give the place and route software sufficient margin to route the design and still stay within your timing requirements.

Simulation data created after the design has been placed, but not routed, contains accurate block delays and estimates for the net delays.

You can use post-place simulation as an incremental simulation step between post-map simulation and a complete post-route timing simulation.

To simulate at any of these intermediate stages, select Tools Simulation/Verification Checkpoint Gate Simulation Control from the Foundation Project Manager and choose the appropriate netlist to simulate.

Creating Functional Simulation Data

For schematic and HDL designs, the functional simulation netlists are created in the Foundation design entry tools environment. Click the Simulation phase button in the Project Manager Flowchart area to invoke the Simulator and load the netlist. The Simulation phase button is shown in the following figure.

For designs that include macros whose underlying files are XNF or EDIF netlists, the design must first be “translated” in the Xilinx implementation tools in order to merge in these additional netlists. Follow these steps to translate the design and then invoke the simulator and load the functional netlist.

1. Select Project Create Version from the Project Manager.
   
   
2. Select Project Create Revision from the Project Manager.
   
   
3. Select Tools Implementation Flow Engine from the Project Manager, while the new revision is selected in the Versions tab.
   
   
4. From within the Flow Engine, select Setup Stop After and then choose the Stop After Translate option.
   
   
5. Click OK, then select File Run in the Flow Engine.
   
   
6. After Translate is complete, go back to the Foundation Project Manager and select Tools Simulation/Verification Checkpoint Gate Simulation Control.
   
   
7. Choose the appropriate NGD file from the Revision which was just created and click OK. This invokes the simulator and loads the netlist.
   
   

For details about functional simulation, refer to the “Functional Simulation” chapter in the Foundation Series User Guide and the “In-Depth Tutorial - Functional Simulation” chapter in this manual, the Quick Start Guide.

For additional information about functional simulation, see the “Performing Functional Simulation” section of the “Design Methodologies - Schematic Flow” chapter in the Foundation Series User Guide.

Creating Timing Simulation Data

Before you perform timing simulation, ensure that you have generated a timing annotated simulation netlist. See the “Timing Simulation” section of the “Verification and Programming” chapter in the Foundation Series User Guide for details and the “In-Depth Tutorial - Timing Simulation” chapter in this manual, the Quick Start Guide.

1. To create the timing simulation netlist, open the Options dialog box, and select the Produce Timing Simulation Data option.
   
   
2. Click OK.
   
   
3. After the Implementation process is complete, return to the Foundation Project Manager, and click the timing simulation portion of the Verification phase button. This invokes the Simulator and loads the timing simulation netlist.
   
   
   
   

For additional information about timing simulation, refer to the “Verifying the Design” section of the “Design Methodologies - Schematic Flow” chapter in the Foundation Series User Guide.