You can perform functional simulation before design implementation to verify that the logic that you have created is correct. Foundation provides a Logic Simulator, which is a gate-level simulator. You can perform functional simulation on a schematic-based design immediately after the design is captured in the Schematic Capture tool. In the case of an HDL-based design, you can perform functional simulation immediately following synthesis. In a later section, you can perform timing simulation, which takes place after the design is implemented (placed and routed) with the Xilinx Implementation Tools.
This chapter contains the following sections.
