This chapter guides you through a typical FPGA schematic-based design procedure using a design of a runner's stopwatch called “Watch”. The design example used in this tutorial demonstrates many device features, software features, and design flow practices that you can apply to your own design. The Watch design targets an XC4000E device; however, all of the principles and flows taught are applicable to any Xilinx device family, unless otherwise noted.
For an example of how to design with CPLDs, see the online help by selecting Help 
Foundation Help Contents from the Project Manager. Under Tutorials, select CPLD Design Flows.
In the first part of the tutorial, you will use the Foundation design entry tools to complete the design. The design is composed of schematic elements, a state machine, a LogiBLOX component, and an HDL macro. After the design is successfully entered in the Schematic Editor, it is ready for functional simulation with the Foundation Logic Simulator, implementation with the Xilinx Implementation Tools, timing simulation, and, finally, downloading and hardware debugging in a Xilinx FPGA on the FPGA Demonstration Board. This board is not supplied with Foundation. To obtain a board, contact your local Xilinx sales representative.
These implementation, simulation, and downloading portions of the tutorial can be found in the subsequent tutorial chapters.
If you use Verilog or VHDL to create an HDL macro, then you must have Base Express or Foundation Express and a valid license.
This chapter includes the following sections.
