Previous

Synthesizing the Design

Now that the design has been entered and analyzed, the next step is to synthesize the design. In this step, the HDL files are translated into gates and optimized to the target architecture.

  1. Set the global synthesis options by selecting Synthesis Options. Set the Default Frequency to 20MHz, and check the Export Timing Constraints box. Click OK to accept these values.

  2. Click the + next to STOPWATCH.VHD (or STOPWATCH.V). This shows the entities (or modules) within the HDL file. Some files may have multiple entities (or modules).

  3. Right click the entity named “stopwatch” and select Synthesize.



    This step can also be done by clicking the Synthesis button under the flow tab. Select the stopwatch entity or module by using the pulldown in the Top Level field. Be sure that the Version Name field has an entry.

  4. Complete the Target Device fields with this information:

  5. Check the boxes labeled Edit Synthesis/Implementation Constraints and View Estimated Performance after Optimization.

    Selecting the Edit Synthesis/Implementation Constraints box automatically opens the Express Constraints Editor after synthesis is complete.

    Selecting the View Estimated Performance after Optimization box automatically opens the Optimized dialog box which displays the results of the synthesis and optimization.

    Figure 5.13 Synthesis/Implementation Window

  6. Click Run. Express synthesizes the design and opens the Express Constraints Editor.

    NOTE

    The Express Constraints Editor is not available to non-registered users or with Base Express licenses. All the functionality covered by the Express Constraints Editor can be achieved by component instantiation (Pullups, Pulldowns, Clock Buffers, I/O Flip Flops), UCF file (timing constraints, pin location constraints), or MAP options (merging flip flops into IOBs). If you are a Base Express customer, skip to the “In-Depth Tutorial - Functional Simulation” chapter.

Next