Testing the Design Using a Demonstration Board

The FPGA demonstration board includes both an XC3000 family socket and an XC4000 family socket. This tutorial only targets the XC4000 family.

Figure 9.1 FPGA Demonstration Board Components

Preparing the Design for Readback

If you are verifying the schematic design, be sure that you have placed the DEBUG_CKT macro in your design as explained in the “Hardware Verification -- Startup and Readback (Optional)” section of the “In-Depth Tutorial - Schematic-Based Design” chapter of this tutorial in order to enable the Readback functionality. (The HDL design already contains the DEBUG_CKT macro.) This step is not necessary if you intend only to perform design download and not readback verification.

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Figure 9.2 DEBUG_CKT Symbol Connections

The DEBUG_CKT macro provides three functions used in debugging the Watch design: Readback, Startup, and clock Mux. These are not all necessary but are offered as examples for accommodating in-circuit testing.

• The READBACK Symbol
  
  The following figure shows a detailed view of the READBACK symbol and its connections.
  
  

  Figure 9.3 Readback Symbol Connections

  The READBACK symbol is the only necessary component for enabling readback verifying and capturing features. While the TRIG and DATA signals could be routed to any user I/Os, the MD0 and MD1 signals are used, respectively. These two signals (MD0 and MD1) are connected to the J2 header pins on the demonstration board to simplify the XChecker cable connections to the RT and RD Flying Leads, respectively.
  
  
• The STARTUP symbol
  
  

  Figure 9.4 STARTUP Symbol Connections

  The STARTUP symbol provides access to the GSR (Global Set Reset) net which when asserted re-initializes all the flip-flops in the FPGA. For debugging purposes, this will be connected to the RST Flying Lead so that the Hardware Debugger can assert a global reset. In this design, the connection to the GSR is inverted because the GSR pin is active HIGH while the RST pin of the XChecker cable is active LOW. The GRST input signal is constrained to P56 so that the RESET button of the demonstration board may also be used to assert the GSR.
  
  
• Clock MUXing network
  
  

  Figure 9.5 Clock Muxing Circuitry

  The Watch design uses the internal FPGA oscillator (OSC4) as the system clock. Synchronous debugging requires interrupting this connection so that the clock input may be driven by the cable and thus controlled by the Hardware Debugger. This demonstrates good design practice when multiplexing clock signals in an FPGA.
  
  Though the Watch design is a low speed application that would not be critically affected by clock “glitching”, it is generally considered poor design practice to “gate” clocks. Therefore, a flip-flop registers the output of the MUX2 to remove glitching and restore the clock phase. The select (S0) of the MUX2 is registered for switch debouncing. There are many other clock multiplexing methods that may be better for other applications.
  
  The CLK_SELECT input is constrained to Pin 27 of the XC4003E. This site can be controlled by the SW3-7 switch on the demonstration board. Placing this switch in the open position will select the internal oscillator for the system clock. Closing this switch selects an external clock located at P13. This external clock input can then be driven by the CLKO flying lead of the XChecker cable and thus controlled by the Hardware Debugger.
  
  

Generating a Bitstream

You have already created the bitstream for this design when you implemented the design in the “In-Depth Tutorial - Design Implementation” chapter. You will use this bitstream file to configure the FPGA on the Xilinx demonstration board.

Connecting the Cable

To load the configuration bitstream to the demonstration board, you need one of the three available hardware cables: an XChecker cable, a parallel cable, or a serial cable. All three cables work with any of the Xilinx demonstration boards; however, the XChecker cable is the only cable that supports readback verification and debugging.

Before physically downloading the design into the FPGA on a Xilinx demonstration board, you must correctly hook up the board to your computer.

You must also connect several control and power pins between the board and the cable. The bundles of leads supplied with the cables are labeled to help you connect the board to the cable.

Finally, you must connect a pair of power and ground pins to a regulated 5 volt power supply to provide power to the board and cable.

1. Plug one end of the cable into the back of your computer.
   
   If you are using a parallel cable, attach the cable to a parallel port. If you are using a serial cable or the XChecker cable, connect the cable to a serial port.
   
   
2. Connect the other end of the cable to your demonstration board. If using the XChecker cable, you should have two different sets of jumpers available.
   
   “Flying Leads” are bound and keyed at one end, and separate and labeled at the other. Flying Leads are shipped with each cable type.
   
   “XChecker Jumpers” are bound and keyed at both ends. They are shorter than the flying leads and are not labeled. XChecker Jumpers are only shipped with the demonstration board.
   
   To download the Watch Tutorial, Xilinx recommends using the Flying Leads since using the XChecker Jumpers requires some additional jumpers not supplied. However, in general to download to the demonstration board, the XChecker Jumpers are a fast and easy method for attaching the XChecker Cable.
   
   Cable connections to download to the demonstration board are shown in the following table.
   
   

   Table 9_1 Cable Connections (Downloading)

   Cable Label	FPGA Board (XC4000E)
   VCC	J2-1
   GND	J2-3
   No Connection	J2-5
   CCLK	J2-7
   D/P	J2-9
   DIN	J2-11
   XChecker and Serial Download Cable
   PROG	J2-13
   XChecker Cable Only
   INIT	J2-15
   RST	J2-17 (Pin 56)

   
   
   
   

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   NOTE

   The RST connection is not necessary for downloading XC4000 designs. This connection is used by the Hardware Debugger for resetting the FPGA design after configuration. If you are using the Flying Lead connectors, then connect the RST lead to Pin 56 of the XC4003E. To make this connection if you are using the XChecker Jumpers, you must close the J7 jumpers on the demonstration board.

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   The “FPGA Design Demonstration Board” chapter of the Hardware User Guide discusses in detail the demonstration board and how to hook it up.
   
   
3. Connect the RT and RD pins, which are used for triggering and capturing readback data. Refer to the following table for pin location information.
   
   
   
   

   Table 9_2 Cable Connections (Verification and Debugging)

   XChecker Cable Label	FPGA Board (XC4000E)
   CCLK	J2-7
   RT	J2-2
   RD	J2-4
   TRIG	J2-6
   CLKI	J2-16
   CLKO	J2-18 (Pin 13)

   
   
   
   
4. Connect the CLKO lead to Pin 13 of the XC4003E. The CLKI and TRIG lead can be left unconnected.
   
   

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   NOTE

   For synchronous debugging, if you are using the XChecker Jumpers, then another jumper connection must be made from J10 Pin 3 to Pin 13.

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5. Ensure that the power supply is connected to the demonstration board at J9 and is turned on.
   
   The power connections for the demonstration board are shown in the following table.
   
   

Table 9_3 Demonstration Board Power Connections

Make sure the FPGA demonstration board is set up for slave mode configuration. The configuration mode for the XC4000E family part is controlled by the SW2 bank of switches. Set the switches as shown in the following table.

Table 9_4 SW2 Switch Settings for XC4000E Configuration

NOTE

The RST switch SW2-7 must be Open in order to configure the XC4000E device without disturbing the XC3000 if it has already been configured. However, this tutorial utilizes only the XC4000E, and the Watch design requires this connection to be Closed so that the RESET button is connected to the GSR input at Pin 56.