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Process Statements

A process statement contains an ordered set of sequential statements. The syntax follows.

   [ label: ] process [ ( sensitivity_list ) ]    
         { process_declarative_item }    
    begin    
         { sequential_statement }    
    end process [ label ] ;

An optional label names the process. The sensitivity_list is a list of all signals (including ports) read by the process, in the following format.

   signal_name {, signal_name}

The hardware synthesized by Foundation Express is sensitive to all signals read by the process. To guarantee that a VHDL simulator sees the same results as the synthesized hardware, a process sensitivity list must contain all signals whose changes require simulating the process again. Foundation Express checks sensitivity lists for completeness and issues warning messages for any signals that are read inside a process but are not in the sensitivity list. An error is issued if a clock signal is read as data in a process.

NOTE

IEEE VHDL does not allow a sensitivity list if the process includes a wait statement.

A process_declarative_item declares subprograms, types, constants, and variables local to the process. These items can be any of the following items.

Each sequential_statement is described in the “Sequential Statements” chapter.

Conceptually, the behavior of a process is defined by the sequence of its statements. After the last statement in a process is executed, execution continues with the first statement. The only exception is during simulation; if a process has a sensitivity list, the process is suspended (after its last statement) until a change occurs in one of the signals in the sensitivity list.

If a process has one or more wait statements (and therefore no sensitivity list), the process is suspended at the first wait statement whose wait condition is FALSE.

The hardware synthesized for a process is either combinatorial (not clocked) or sequential (clocked). If a process includes a wait or if signal'event statement, its hardware contains sequential components. The wait and if statements are described in the “Sequential Statements” chapter.

NOTE

Process statements provide a natural means for describing conceptually sequential algorithms. If the values computed in a process are inherently parallel, consider using concurrent signal assignment statements. (See the “Concurrent Signal Assignments” section of this chapter).

Combinatorial Process Example

The following example shows a process that implements a simple modulo-10 counter. The example process is sensitive to (reads) two signals: CLEAR and IN_COUNT. The process drives one signal, OUT_COUNT. If CLEAR is '1' or IN_COUNT is 9, then OUT_COUNT is set to zero. Otherwise, OUT_COUNT is set to one more than IN_COUNT. The resulting circuit is shown in the figure following the example.

   entity COUNTER is     
       port (CLEAR:      in BIT;    
             IN_COUNT:   in INTEGER range 0 to 9;    
             OUT_COUNT: out INTEGER range 0 to 9);    
    end COUNTER;    
    
   architecture EXAMPLE of COUNTER is    
    begin    
      process(IN_COUNT, CLEAR)    
      begin    
         if (CLEAR = '1' or IN_COUNT = 9) then    
            OUT_COUNT <= 0;    
         else    
            OUT_COUNT <= IN_COUNT + 1;    
         end if;    
      end process;    
    end EXAMPLE;

Figure 7.1 Circuit for Modulo-10 Counter Process

Sequential Process Example

Because the process in the example of the Modulo-10 counter process contains no wait statements, it is synthesized with combinatorial logic. An alternate implementation of the counter is to retain the count value internally in the process with a wait statement.

The following example shows an implementation of a counter as a sequential (clocked) process. On each 0-to-1 CLOCK transition, if CLEAR is '1' or COUNT is 9, COUNT is set to zero; otherwise, COUNT is incremented by 1. The resulting circuit is shown in the figure that follows the example.

   entity COUNTER is     
       port (CLEAR: in BIT;    
             CLOCK: in BIT;    
             COUNT: buffer INTEGER range 0 to 9);    
    end COUNTER;    
    
   architecture EXAMPLE of COUNTER is    
   begin    
      process    
      begin    
         wait until rising_edge;    
    
         if (CLEAR = '1' or COUNT >= 9) then    
            COUNT <= 0;    
         else    
            COUNT <= COUNT + 1;    
         end if;    
      end process;    
    end EXAMPLE;

Figure 7.2 Circuit for Modulo-10 Counter Process with wait Statement

In the example of the Modulo-10 counter process with wait Statement, the value of the variable COUNT is stored in four flip-flops. These flip-flops are generated because COUNT can be read before it is set, so its value must be maintained from the previous clock cycle. See the “Wait Statements” section of the “Sequential Statements” chapter for more information.

Driving Signals

If a process assigns a value to a signal, the process is a driver of that signal. If more than one process or other concurrent statement drives a signal, that signal has multiple drivers.

The following example shows two three-state buffers driving the same signal (SIG). The resulting circuit is shown in the figure following the example. The “Three-State Inference” section of the “Register and Three-State Inference” chapter shows how to describe a three-state device in technology independent VHDL. 

   A_OUT <= A when ENABLE_A else 'Z';    
   B_OUT <= B when ENABLE_B else 'Z';    
    
   process(A_OUT)    
   begin    
       SIG <= A_OUT;    <
   end process;    
    
   process(B_OUT)    
   begin    
       SIG <= B_OUT;    
   end process;

Figure 7.3 Circuit for Multiple Drivers of a Signal

Bus resolution functions assign the value for a multidriven signal. See the “Resolution Functions” section of the “Describing Designs” chapter for more information.

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