XC9500 HDL-ABEL Synthesis Tools

WebPACK HDL_ABEL Version 2.1WP2.1

WebPACK is a free, downloadable, modular design entry and implementation system for developing Xilinx CPLD designs on PCs.

The HDL_ABEL module is used to compile VHDL, Verilog and ABEL language designs into EDIF netlists that can be implemented on Xilinx devices in the following ways:

• Implemented directly on a CPLD using the WebPACK CPLD_Fitter module.
• Implemented directly on a CPLD using the WebFITTER web-based CPLD fitter.
• Embedded in a schematic design prepared using a supported Xilinx Alliance EDA tool. The whole design can then be implemented on a Xilinx device using:
  • WebPACK CPLD_Fitter module's Design Manager user interface (CPLDs only).
  • WebFITTER (CPLDs only).
  • Xilinx Alliance software (any Xilinx device).

The HDL_ABEL module is compatible and can be use with any of the following other WebPACK modules:

• CPLD_Fitter Version 2.1WP2.x: The XC9500-series CPLD fitter.
   
• Programmer Version 2.1WP2.x: JTAG download software for programming Xilinx CPLDs.

  Note: Differences in the last field of the version string ("x" above) do not impact compatibility between WebPACK modules.

The HDL_ABEL module consists of the following application programs:

• ABEL compiler, Version 7.10, including Blifsim functional simulator.
• Project Navigator, Version 5.0, including simulation waveform viewer.
• XST HDL compiler, Version 6.2.

Note: Xilinx software "Service Packs" do not apply to WebPACK software. Any and all updates to WebPACK software are included in periodic revisions of the original WebPACK download modules.

To review the known issues for this module, refer to the HDL_ABEL Release Notes.

To view the revision history for this module, refer to the HDL_ABEL Revision History for KOREAN.
 

Quick Start Design Guide

These are the basic steps for processing a design using the WebPACK HDL_ABEL and CPLD_Fitter modules combined:

1. Create a New Project

Create a new design in an existing or newly created folder by selecting File -> New from the Project Navigator pulldown menu.

Click Here for details on creating a new project.

2. Open or Create Source File(s)

Select Source -> Add or Source -> New from the Project Navigator pulldown menu to add or create the source files for the design.

Click Here for details on creating a new source design.

3. Select Target Device

Double-click the targeted device icon as shown below and choose the CPLD family (vendor name) and device that you wish to target.

Click Here for details on selecting a target device.

4. Fit Design

With the target device highlighted, double click the Fit Design icon as shown below.

Click Here for details on fitting the design.

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