Controlling Logic Optimization

The fitter normally attempts to collapse (flatten) as much combinatorial logic as possible into the smallest number of CPLD macrocells. Collapsing generally improves speed and density at the same time.

When a larger combinational function with several AND-OR logic levels is completely collapsed, the number of product terms required to implement the function may grow considerably. By default, the fitter limits the number of p-terms used as a result of collapsing (after Boolean reduction) to 25. If the result of collapsing would exceed this p-term limit, then collapsing is not performed and the function is implemented using two or more levels of AND-OR logic. Furthermore, if the Use Timing Optimization option is disabled in the XC9500 Optimization Options menu, the fitter will only collapse a node if the total number of p-terms is reduced as a result of collapsing.

If the resulting path delay of a large, multi-level logic function is not satisfactory, try increasing the p-term limit to allow it to be flattened further. To do this, increase the Collapsing Pterm Limit in the Advanced tab of the XC9500 Implementation Options window . For example, you may try increasing the Collapsing Pterm Limit to 35 or 45 when rerunning the fitter. To set Pterms see Setting Pterms from Project Navigator or Setting Pterms from Design Manager depending on which interface you are using.

The fitter report (design_name.rpt) indicates the number of p-terms used for each logic function. You should see these numbers increase as you raise the p-terms limit, until the design is fully flattened. At the same time, you will see the internal combinational nodes eliminated until none remain.

Some designs which fit the target device initially may fail to fit if flattened too much. If you cannot increase the p-term limit enough to sufficiently flatten a critical path and still fit the target device, you may try applying the KEEP logic optimization control attribute to specific non-critical nodes in your design. Applying KEEP to a logic node or its output net prevents collapsing of that node into its fan-outs, which may reduce the number of p-terms used by your design. If you set the p-term limit too high and your design no longer fits, try using KEEP to reduce the size of selected non-critical paths.

You can also force a logic node to collapse into all of its fanouts by applying the COLLAPSE attribute to the logic node. You could use the COLLAPSE attribute to flatten and speed up a logic path beyond the Collapsing Pterm Limit. If you want to force collapsing across a multi-gate logic chain, you may need to use multiple COLLAPSE attributes.

In VHDL designs, apply the signal_preserve attribute to a net in the source file using the following syntax:

entity example is

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.
.
attribute signal_preserve : string; end example;
architecture arch of example is

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signal net_name : std_logic;
attribute signal_preserve of net_name : signal is "yes"; begin

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. end arch;

In Verilog designs, apply the KEEP attribute to a net in the source file using the following syntax:

NET net_name KEEP;

In VHDL or Verilog designs, apply the COLLAPSE attribute to a net in the UCF file using the following syntax:

NET net_name COLLAPSE;

In ABEL designs, use the KEEP attribute in the ABEL node declaration to preserve a logic node through both ABEL compilation and CPLD implementation. The syntax of the node declaration is:

node_name Node istype ‘KEEP’;

If you use the ABEL attribute COLLAPSE in a node declaration, the ABEL compiler will collapse the node before netlisting. For example:

node_name Node istype ‘COLLAPSE’;

If, instead, you want to pass the logic node to the fitter and force the fitter to collapse the node, do not use the COLLAPSE attribute in the ABEL design. Instead, apply the COLLAPSE attribute to the net in the UCF file using the syntax:

NET net_name COLLAPSE;