Controlling Power Consumption
You can set your default power consumption in the Fit Design Properties dialog of the Project Navigator, or from Implementation Options window of the Design Manager. The default for new projects is Standard (Std). The other options are Low and Timing Driven.
If you are using timing contraints, you can use timing driven automatic power reduction to automatically reduce power on paths that can meet speed while still operating in low power. In this mode, the software uses timing driven optimization to implement the design, then selectively reduces power wherever possible and still meet the required timing.
You can control power consumption for specific macrocells with the PWR_MODE attribute. Use PWR_MODE to selectively control whether specified logic operates in high speed or low power mode.
Controlling Power Consumption in ABEL
Controlling Power Consumption in VHDL or Verilog