Controlling Slew Rate
Each output of a CPLD device can be programmed to operate at full speed (FAST) or with limited slew rate (SLOW). Limiting the slew rate reduces output switching surges, which becomes important when your design uses a large number of outputs or when you have edge-rate sensitive transmission lines on your board.
If you are using timing constraints, the software can automatically reduce the slew rate on pins that can meet their speed requirements while still operating in slew rate limited mode. In this mode, the software uses timing driven optimization to implement the design, then selectively reduces output slew rate wherever possible (while meeting the required timing).
You can control slew rate for specific output or I/O pins with the FAST and SLOW attributes. Use these attributes to selectively control whether specific pins operate in fast slew rate (FAST) or slew rate limited (SLOW) mode.
Using FAST and SLOW in VHDL or Verilog