Istype 'reg'
Clocked Memory Element

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg' ;

Use

Signal attribute 'reg' indicates that the associated signal has a D-type flip-flop as its memory element. Since flip-flop types are normally determined by the use of ':=' or by the use of dot extensions (.D, .T, etc.) in equations, the 'reg' attribute is only significant when state diagrams are used. When 'reg' is specified, the equations resulting from an ABEL-HDL state diagram will be pin-to-pin registered equations (the same as if you had written equations using ':='). You do not need to worry about the existence of inverted output pins.