Istype 'reg_G'
D Flip-flop Gated Clock Memory Element

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_g' ;

Use

Signal attribute 'reg_G' indicates that the associated signal has a D-type flip-flop with enabled clock as its memory element. Equations generated from an ABEL-HDL state diagram will assume this register type if the 'reg_g' attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures.

This register type is emulated in Xilinx CPLDs by multiplexing the flip-flop data input and Q feedback, as selected by the clock enable input.