Speeding Up tSU with Local Feedback

Use timing constraints to specify tSU . The timing constraint to specify pad-to-pad setup time from pad A to flip-flop RegY would look like:

TS01=FROM:PADS(A):TO:FFS(RegY):10

Or, you could directly specify the actual desired tSU in the UCF file using the following OFFSET timespec:

NET A OFFSET=IN:7:BEFORE:Clock;

See Using Timing Constraint Driven Optimization for a complete description of how to use timing constraints for CPLD designs.

The fitter will attempt to group the data-path logic function and registers into the same function block to use the local feedback path between them. If you need to explicitly group flip-flop RegY and the combinatorial logic between the input pad and the flip-flop that was not optimized (resulting in multi-level logic between the input and the flip flop) into the same function block, you could use the LOC property. To place RegY and the un-optimized logic represented by GATE in function block 1 the required LOC properties would look like this:

Using ABEL:

The BLOCK property can be used to apply an arbitrary attribute string, such as the LOC attribute, to an individual design element in the netlist from ABEL.

xilinx property ‘BLOCK RegY LOC=FB1’;

xilinx property ‘BLOCK GATE LOC=FB1’;

Using UCF File (for VHDL or Verilog designs):

INST RegY LOC=FB1;

NET GATE LOC=FB1;