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Using Path Filtering Commands

By default, the Custom Analysis reports the path delays for all paths in the design. However, you can instruct the Timing Analyzer to analyze and report on a subset of paths by using commands in the Path Filters menu and it submenus.

The Path Filters menu consists of the Reset All Path Filters command and the Timing Constraint Filters, Custom Filters, and Common Filters submenus.

The types of commands contained in these submenus are described in the “Path Filtering Commands” section of the “Introduction” chapter. Also, see the “Specifying Report Appearance and Content” section for information on report format and general content customizing.

After using these commands to specify specific paths and to apply filters, you can generate reports using the commands in the Analyze menu. Refer to the “Creating Reports” section for more information on report generation.

The procedures in the following sections often direct you to specify a filter in a dialog box or to move items between list boxes. Refer to the “Using Filters with Commands” section and the “Moving Items in List Boxes” section of the “Getting Started” chapter for detailed instructions on specifying a filter and on selecting and moving items between list boxes.

Timing Constraint Filters

The Timing Constraints Filters submenu contains the Disable Timing Constraints command which you can use to prevent the Timing Analyzer from analyzing specific timing constraints. These commands function only if a design is loaded. They do not alter the Advanced Design Analysis report or the Custom Analysis report.

To prevent the Timing Analyzer from analyzing specified timing constraints, perform the following steps.

  1. Select Path Filters Timing Constraint Filters Disable Timing Constraints.

    The Disable Timing Constraints dialog box appears, as shown in the “Disable Timing Constraints Dialog Box” figure of the “Menu Commands” chapter.

    NOTE

    If an FPGA design is open, the Include PCF Entered Constraints radio button is selected by default. Click the Omit PCF Entered Constraints radio button, if you want to include user constraints during analysis. User constraints are contained in the “USER” section of the PCF. These two buttons and their functions are only visible and available for FPGAs.

  2. If you would like to display a subset of timing constraints, enter a filter string in the Filter field and click Apply.

    The subset of timing constraints is displayed in the Enabled Constraints list box. See the “Using Filters with Commands” section of the “Getting Started” chapter for valid filter inputs.

  3. Select the timing constraints you want to exclude from the Timing Constraints Analysis report in the Enabled Constraints list box and move specific ones or all of them to the Disabled Constraints list box.

    See the “Moving Items in List Boxes” section of the “Getting Started” chapter for instructions on moving items between list boxes.

  4. Click OK.

    The Disable Timing Constraints dialog box closes. You can now select another command or generate a Timing Constraints Analysis report.

Custom Filters

You can select starting points and ending points using commands described in this section to specify the scope of path analysis information reported in the Custom Analysis report. These commands are in the Custom Filters submenu of the Path Filters menu. By default, the Timing Analyzer selects all sources and all destinations for path analysis.

Selecting Sources

To select specific sources for path analysis, follow these steps.

  1. Select Path Filters Custom Filters Select Sources.

    The Select Sources dialog box appears, as shown in the “Select Sources Dialog Box” figure of the “Menu Commands” chapter.

  2. Select the source type by clicking the down arrow of the Source Element Type pull-down list box to display the list of sources, then highlight it. The default is Flip-Flops.

    FPGA source types can be flip-flops, RAMs, latches, pads, nets, pins, CLBs, or clocks. CPLD destination types can be flip-flops, pads, nets, macrocells, or clocks.

    Element in the Filter field and the Source Element list box changes to match the source type you select.

  3. If you select Clocks, specify the type of clock edge by clicking the down arrow and highlighting the selection in the Clock Edge field. Clocks are only supported for FPGA designs. These are the Clock Edge options.

  4. Enter some text in the Filter field to display a subset of the specified source type, if desired, and click Apply. See the “Using Filters with Commands” section of the “Getting Started” chapter for valid filter inputs.

  5. Select the sources you want to include in Timing Analysis from the Source Element list box and move specific ones or all of them to the Selected Sources list box.

    See the “Moving Items in List Boxes” section of the “Getting Started” chapter for instructions on moving items between list boxes. The Select Sources dialog box utilizes a special way of representing nets in the Source element_type and Selected Sources list boxes. The list boxes contain *All* or *All* [element_type] to represent all the nets in a category. For example, if you select *All* in the Source Flip-Flops list box and move it to the Selected Sources list box, it appears as *All* [Flip-Flops] to indicate that all the Flip-Flops are selected. You get the same result if you individually move all the Flip-Flop nets from the Source Flip-Flops to the Selected Sources list box.

  6. Repeat steps 2 through 5 until you have moved all the desired types of elements to the Selected Sources list box.

  7. Click OK.

    The Select Sources dialog box closes. You can now select another path filtering command or generate a timing report.

Selecting Destinations

To select specific destinations for path analysis, follow this procedure.

  1. Select Path Filters Custom Filters Select Destinations.

    The Select Destinations dialog box appears, as the “Select Destinations Dialog Box” figure of the “Menu Commands” chapter illustrates.

  2. Select the ending point type by clicking the down arrow of the Destination Element Type pull-down list box to display the list of destinations, then highlight it. The default is Flip-Flops.

    FPGA destination types can be flip-flops, RAMs, latches, pads, nets, pins, CLBs, or clocks. CPLD destination types can be flip-flops, pads, nets, macrocells, or clocks.

    Element in the Destination Element list box changes to match the destination type you select.

  3. If you select Clocks, specify they type of clock edge by clicking the down arrow and highlighting the selection in the Clock Edge field. Clocks are only supported for FPGA designs. These are the Clock Edge options.

  4. Enter some text in the Filter field to display a subset of the specified source type, if desired, and click Apply. See the “Using Filters with Commands” section of the “Getting Started” chapter for valid filter inputs.

  5. Select the destinations you want to include in Path Analysis from the Destination Element list box and move specific ones or all of them to the Selected Destinations list box.

    See the “Moving Items in List Boxes” section of the “Getting Started” chapter for instructions on moving items between list boxes. The Select Destinations dialog box utilizes a special way of representing nets in the Destination element_type and Selected Destinations list boxes. The list boxes contain *All* or *All* [element_type] to represent all the nets in a category. For example, if you select *All* in the Destination Flip-Flops list box and move it to the Selected Destinations list box, it appears as *All* [Flip-Flops] to indicate that all the Flip-Flops are selected. You get the same result if you individually move all the Flip-Flop nets from the Destination Flip-Flops to the Selected Destinations list box.

  6. Repeat steps 2 through 5 until you have moved all the desired types of elements to the Selected Destinations list box.

  7. Click OK.

    The Select Destinations dialog box closes. You can now select another path filtering command or generate a timing report.

Common Filters

You can include or exclude paths with nets or control path tracing using commands described in this section to specify the scope of timing analysis. These commands exist in the Common Filters submenu of the Path Analysis menu.

Although the Include Paths with Nets and Exclude Paths with Nets commands in the Common Filters submenu appear to be similar, they are not mutually exclusive. For example, you might want to exclude any path that goes through the synchronous Reset net of the counter but include all paths that go through bit 1 of the counter. By using the Exclude Paths with Nets command to exclude the synchronous Reset, and the Include Paths with Nets command to include paths through the bit 1, you can include or exclude specific nets that are attached to the counter.

After using the path filtering commands in the Common Filters submenu, you can generate a Timing Constraints Analysis, Advanced Design Analysis, or Custom Analysis report.

Including Paths with Nets

Use the Include Paths with Nets command to limit analysis to paths that contain specified nets. If a net is not selected, paths through that net are not analyzed. However, if no nets are selected, which is the default, all paths, except those subject to other filtering commands, are analyzed. To select nets to be included for analysis, use this procedure.

  1. Select Path Filters Common Filters Include Paths with Nets.

    The Include Paths with Nets dialog box appears, as shown in the “Include Paths with Nets Dialog Box” figure of the “Menu Commands” chapter.

  2. Enter some text in the Filter field to display a subset in the Available Nets list box, if desired, and click Apply.

    See the “Using Filters with Commands” section of the “Getting Started” chapter for valid filter inputs.

  3. Select the nets that you want to include in your timing analysis from the Available Nets list box and move specific ones or all of them to the Selected Nets list box.

    See the “Moving Items in List Boxes” section of the “Getting Started” chapter for instructions on moving items between list boxes.

  4. Click OK.

    The Include Paths with Nets dialog box closes. You can now select another path filtering command or generate a timing report.

Excluding Paths with Nets

Use the Exclude Paths with Nets command to exclude paths containing specific nets from analysis, regardless of which paths are specified in the Include Paths with Nets command or other filters. If a net is selected, paths through that net are not analyzed. The default does not exclude any nets from analysis. To exclude specific nets from analysis, use this procedure.

  1. Select Path Filters Common Filters Exclude Paths With Nets.

    The Exclude Paths with Nets dialog box appears, as shown in the “Exclude Paths with Nets Dialog Box” figure of the “Menu Commands” chapter.

  2. Enter some text in the Filter field to display a subset in the Available Nets list box, if desired, and click Apply.

    See the “Using Filters with Commands” section of the “Getting Started” chapter for valid filter inputs.

  3. Select the nets that you want to exclude from your timing analysis from the Available Nets list box and move specific ones or all of them to the Selected Nets list box.

    See the “Moving Items in List Boxes” section of the “Getting Started” chapter for instructions on moving items between list boxes.

  4. Click OK.

    The Exclude Paths with Nets dialog box closes. You can now select another path filtering command or generate a timing report.

Controlling Path Tracing

Use the Control Path Tracing command to enable or disable path analysis through delay path types for specific components, such as latches, RAMs, and TBUFs. These paths may be irrelevant to your analysis.

NOTE

This command only applies to FPGAs; it is disabled if a CPLD design is open. (CPLD path timing analysis ignores paths through Set/Reset logic and breaks paths at bidirectional I/O pins.)

After specifying which path types to control through which components, you can generate a Timing Constraints Analysis, Advanced Design Analysis, or Custom Analysis report. Use the following procedure to specify path types through components for path analysis.

  1. Select Path Filters Common Filters Control Path Tracing.

    The Timing Analyzer displays the Control Path Tracing dialog box, illustrated in the “Control Path Tracing Dialog Box” figure of the “Menu Commands” chapter.

  2. Select the path type that you want to control from the Path Type pull-down list box. Click on the down arrow, then highlight one of the path types. The following types are available; see the “Control Path Tracing (Path Filters Menu)” section of the “Menu Commands” chapter for details on these path types.

  3. Enter some text in the Filter field to display a subset of components of the specified type, if desired, and click Apply.

    The Filter changes to match the default state of the path type. See the “Using Filters with Commands” section of the “Getting Started” chapter for valid filter inputs.

  4. Select the components that you want to enable or disable by moving them from the Enabled Components to the Disabled Components list box or vice versa.

    See the “Moving Items in List Boxes” section of the “Getting Started” chapter for instructions on moving items between list boxes.

  5. Click OK.

    The Control Path Tracing dialog box closes. You can now select another filtering command or generate any timing report.

Resetting Path Filters to Defaults

You can reset all of the path filters to the design default settings. After opening a design, select Path Filters Reset All Path Filters. To then view those default settings, select View Settings.

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