Virtex Implementation Options

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the options described in the following sections.

• “Virtex Translate Tab”
  
  
• “Virtex Optimize and Map Tab”
  
  
• “Virtex Place and Route Tab”
  
  
• “Virtex Timing Reports Tab”
  
  

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

Virtex Translate Tab

Use this tab, shown in the following figure, to set the translate options.

Figure 5.22 Virtex Translate Tab

The Virtex Translate tab is identical to the tab described in the “Spartan Translate Tab” section.

Virtex Optimize and Map Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.23 Virtex Optimize and Map Tab

Logic Optimization Options

The Logic Optimization Options group box contains the following options.

• Trim Unconnected Logic
  
  Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.
  
  
• Replicate Logic to Allow Logic Level Reduction
  
  Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.
  
  

Map Options

• Pack I/O Registers/Latches into IOBs for
  
  This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.
  
  
  • Inputs Only
    
    Select Inputs Only to pack flip-flops or latches into input I/O cells.
    
    
  • Outputs Only
    
    Select Outputs Only to pack flip-flops or latches into output I/O cells.
    
    
  • Inputs and Outputs
    
    Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.
    
    
  • Off
    
    Select Off to pack flip-flops or latches as specified by your design entry method.
    
    
• Ignore RLOC Constraints
  
  Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.
  
  

  Note: To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

• Create Detailed Map Report
  
  Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.
  
  

Virtex Place and Route Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.24 Virtex Place and Route Tab

Router Options

Use the Run _ Routing Passes option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.

Auto runs the router until specific exit conditions are met. At place and route effort levels of 3, 4, or 5, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels of 1 or 2, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. The default is Auto.

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses the timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.

Virtex Timing Reports Tab

Use this tab, shown in the following figure, to set the timing report options.

Figure 5.25 Virtex Timing Reports Tab

The Virtex Timing Reports tab is identical to the tab described in the “Spartan Timing Reports Tab” section.