Functional_block Keyword

Syntax

DECLARATIONS
instance_name FUNCTIONAL_BLOCK module_name
EQUATIONS
instance_name.port_name = signal_name; :

instance_name - A unique identifer for this instance of the functional block in the current source.

module_name - The name of the lower-level source being instantiated.

port_name - The name of an input or output port from the lower-level source.

signal_name - The signal or signal set by which the ports (inputs and outputs) in the lower-level source are referenced for that instance of the source.

Purpose

You use a functional_block declaration in a top-level ABEL-HDL source to instantiate a declared lower-level source and make the ports of the lower-level source accessible in the top-level source. You must declare sources with an interface declaration before you instantiate them with a functional_block statement.

Note: The output of an equation must always be on the left side of the equations.

Note: When a source is instanced by a top-level module, any signal attributes (either explicit or implicit) are inherited by the top-level module signals. Therefore, you do not need to specify ISTYPEs in top-level sources for instantiated signals.

Creating Multiple Instances

You can use the range operator (..) to instantiate multiple instance names of the source. For example,

CNT0..CNT3 functional_block cnt4 ;

creates 4 instances of the submodule cnt4.

Mapping Ports to Signals

Signal names are mapped to port names using equations (similar to wiring the signals on a schematic). You need to specify only the signals used in the top-level source if default values have been specified in the lower-level source interface statement. See Interface (lower-level source) for more information on setting default values.

To specify the signal wiring, map signal names to the submodule port names with dot extension notation. There are three kinds of wire: input, output, and interconnect.

Input Wire

Connects submodule outputs to top-level source inputs.

instance.port = input

Output Wire

Connects top-level source outputs to lower-level source inputs.

output = instance.port

Interconnect Wire

Connects the outputs of one instance of a submodule to another instance's inputs.

instance0.port = instance1.port

Example

module counter;
cnt4 interface (ce, ar, clk -> [q0..q3]); "cnt4's top-level interface declaration. CNT0..CNT3 functional_block cnt4; "Four instances of cnt4

Clk, AR, CE pin;
Q0..Q3 pin;

equations
CNT0.[clk,ar,ce]=[Clk,AR,CE]; "Connecting to Clk, AR, and CE inputs.
[Q0..Q3] = CNT0.[q0..q3] ; "Connecting to Q0..Q3 outputs.
end

Note that the above file instantiates four instances of cnt4, but only one (CNT0) is wired.

Overriding Default Values

You can override the default values given in a lower-level source's interface statement by specifying default equations in the top-level source. For example, if you have specified a default value of 1 for the signal ce in interface cnt4 but in instance CNT0, you want ce to be 0, you would write:

CNT0.ce = 0 ;

This equation overrides the 1 with a 0. If you override the default values, you may want to re-optimize the post-linked design.

Unused Outputs (No Connects)

If you do not want to use a submodule's outputs, you can specify them as No Connects (NC) by not wiring up the port to a physical pin. For example, to make a 3-bit counter out of a 4-bit counter in the top-level module, you might use the following wiring equations:

q2..q0 pin ; "top-level signals
Equations
[q2..q0] = CNT_A.[q2..q0]

See Also

Hierarchy

Interface - Declare Submodules for Hierarchical Design

Interface (top-level source)

Interface (lower-level source)