Interface Keyword (top-level)

Syntax

module_name INTERFACE (input/set[=value]-> output/set :> bidir/set);

module_name - The name of the lower-level module being declared.

input/set[=value] -> output/set :> bidir/set - A list of signals in the lower-level module. Signal names are separated with commas. Use -> and :> to indicate the direction of each port of a functional block.

value - An optional default value for an input that overrides defaults in the lower-level module.

Purpose

The interface keyword declares lower-level modules that are used in the current source and defines the order and default values of their ports (signals). This declaration is used in conjunction with a functional_block declaration for each instantiation of the lower-level module.

Use

If the lower-level module uses the interface keyword to declare signals, the top-level source interface statement must exactly match the signal listing.

CAUTION: Interface declarations cannot contain dot extensions. If you need a specific dot extension across a source boundary (to resolve feedback ambiguities, for example), you must introduce an intermediate signal into the lower-level source to provide the connection to the top-level source. All dot extension equations for a given output signal must be located in the ABEL-HDL source in which the signal is defined. No references to that signal's dot extensions can be made outside of the ABEL-HDL source.

Note: When you instantiate a lower-level source in a top-level source, any signal attributes (either explicit or implicit) are inherited by the top-level source signals that map to the lower-level signals. Do not specify ISTYPEs for instantiated signals.

Example

module top;
cnt4 interface (ce,ar,clk -> [q3..q0])

Map port names to signal names with equations. See Functional_block.

See Also

Hierarchy

Functional_block

Interface (lower-level source)

Interface - Declare Submodules for Hierarchical Designs