Interface Keyword (lower-level source)
module_name
Purpose
The interface declaration is optional for lower-level modules. Use the
interface declaration in lower-level modules to assign a default port list and input
values for the module when instantiated in top-level ABEL-HDL sources. If you
use the interface statement in an instantiated module, you must declare the
signals and sets in the top-level source in the same order and grouping as given
in the interface statement in the lower-level module.
Declaring signals in the lower-level module, although optional, does allow the
compiler to check for signal declaration mismatches and therefore reduces the
possibility of wiring errors.
Declared Signals
Declared signals can be a list of lower-level pins, sets or a combination of
both. The following constraints apply to the different signal types:
Signal Type Constraints
Output Unlisted outputs are interpreted as No connects
If you do not list some signals of the lower-level module in the interface
statement, the following rules apply:
Unlisted Pins Are: The Compiler Interprets Them As:
Outputs No Connects (NC), and they can be removed
Feedback outputs Nodes in the top-level source, following the naming
The following interface statement declares inputs ce, ar, and clk, (giving
default values for two of them) and outputs q3 through q0.
Interface - Declare Lower-level Sources for Hierarchical Designs
Output Enable Control of Lower Level Modules
INTERFACE (input/set[=value] -> output/set [:> bidir/set]);
Input Default values must be binary if applied to an
individual bit, or any positive integer applied to a
set. All inputs must be listed.
(NC). Unlisted, fed-back outputs are interpreted as
nodes in the top-level source following the naming
convention:
those with output enable (OE). If you specify
bidirectional signals, the compiler checks for invalid
wire connections.
CAUTION: Interface declarations cannot contain dot extensions. If you need a
specific dot extension across a source boundary (to resolve feedback ambiguities, for
example), you must introduce an intermediate signal into the lower-level source
to provide the connection to the top-level source. All dot extension
equations for a given output signal must be located in the ABEL-HDL source in which the
signal is defined. No references to that signal's dot extensions can be made
outside of the ABEL-HDL source.
Note: When you instantiate a lower-level source in a top-level source, any signal
attributes (explicit or implicit) are inherited by the top-level source signals
that map to the lower-level signals. Do not specify ISTYPEs for instantiated
signals.
Unlisted Signals
Inputs or Bidirectionals with OE Errors
convention:
Note: Supported default values are 1, 0, or X (don't care). You can give default
values for a set with a positive integer, and each digit of the integer's
binary form supplies the default value for the corresponding signal in the set.
See Also