Hierarchy

Hierarchical CPLD design consists of a top-level source that contains functional blocks that are linked together to create the overall design. The functional blocks that are referenced in the top-level source are placeholders for lower-level logic descriptions, which may in turn contain functional blocks that reference even lower-level logic descriptions. The referencing of a logic description is called “instantiation.”

Using Hierarchy

You use hierarchy declarations in an upper-level ABEL-HDL source to refer to (instantiate) another ABEL-HDL source. To instantiate an ABEL-HDL source file, you need to do the following:

In the lower-level source: (optional)

1. Identify lower-level I/O Ports (signals) with an Interface statement

In the top-level source:

2. Declare the lower-level source with an Interface declaration

3. Instantiate the lower-level source with Functional_block declarations.

To identify I/O ports in the lower-level source:

You identify an ABEL-HDL source's input and output ports with an Interface declaration directly following the Module statement. The Interface statement defines the ports in the lower-level source that are used by the top-level source.

You must declare all input pins in the ABEL-HDL source as ports. You can optionally specify default values of 0, 1, or don't-care.

You do not have to declare all output pins as ports. Any undeclared outputs become no-connects or redundant nodes. Redundant nodes can later be removed from the designs during post-link optimization.

The following source fragment is an example of a lower-level interface statement.

module lower
interface (a=0, [d3..d0]=7 -> [z0..z7]) ;
title 'example of lower-level interface statement ' ...

This statement identifies input a, d3, d2, d1 and d0 with default values, and outputs z0 through z7. For more information, see Interface (lower-level source).

To specify signal attributes:

Attributes specified for pins in a lower-level source are propagated up to the higher-level source. For example, a lower-level pin with an 'invert' attribute affects the higher-level signal wired to that pin, its preset, reset, preload, and power-up value.

Output Enables (OE)

Connecting a lower-level tristate output to a higher-level pin results in the output enable being specified for the higher-level pin. If another OE is specified for the higher-level pin, it is flagged as an error. Since most tristate outputs are used as bidirectionals, it might be important to keep the lower-level OE.

Buried Nodes

Buried nodes in lower-level sources are handled as follows:

Dangling

Lower-level nodes that do not fanout are propagated to the higher-level source and become dangling nodes. Optimization may remove dangling nodes from the lower-level source.

Combinational

Combinational nodes in a lower-level source become collapsible nodes in the higher-level source.

Registered

Registered nodes are preserved with hierarchical names assigned to them.

Declaring Lower-level Source in the Top-level Source

To declare a lower-level source, you match the lower-level source interface statement with an interface declaration. For example, to declare the lower-level source fragment given above, you would add the following declaration to your upper-level source declarations:

lower interface (a=0, [d3..d0]=7 -> [z0..z7]) ;

You could specify different default values if you want to override the ones given in the instantiated source, but otherwise it must match the lower-level interface statement exactly. See Interface (higher-level source) for more information.

Instantiating Lower-level Source in the Top-level Source

You use a functional_block declaration in an top-level ABEL-HDL source to instantiate a declared lower-level source and make the ports of the lower-level source accessible in the upper-level source. You must declare sources with an interface declaration before you instantiate them.

To instantiate the source declared above, add an interface declaration and signal declarations to your top-level declarations, and port connection equations to your top-level equations as shown in the source fragment below:

DECLARATIONS
low1 FUNCTIONAL_BLOCK lower ;
zed0..zed7 pin ; "upper-level outputs
atop pin ; "upper-level input
d3..d0 pin ; "upper-level inputs

EQUATIONS
low1.a = atop; "wire this source's inputs
low1.[d3..d0] = [d3..d0] ; " to lower-level inputs
[zed0..zed7] = low1.[z0..z7]; "wire this source's outputs to
" lower-level outputs

See Functional_block for more information.