Using Global Nets
Clock, output enable, and register set and reset control signals can be
implemented either on special globally routed nets or as ordinary signals through the
p-terms. Control signals assigned to global nets are faster and do not use up
function block resources. By default, the fitter assigns input pads used as
control signals to global nets whenever possible. If you want to prevent the
fitter from automatically using global nets, disable the appropriate option in
the Process Properties dialog of the Project Navigator, or, if you are
using the Design Manager, the Implementation Options window. You may also
assign global nets manually in ABEL or in the UCF for Veriolog and VHDL designs.
Global nets can be assigned to input pads or internal nets. When a global net is
assigned to an internal net, the CPLD Fitter will create an I/O pad for the net so that
it can use the global resources.
See Also
Assigning Global Nets in Project Navigator
Assigning Global Nets in Design Manager
Assigning Global Nets Manually in ABEL
Assigning Global Nets Manually in VHDL or Verilog