Register Inference

By inferring registers, you can use sequential logic in your designs and keep your designs technology-independent. A register is a simple, one-bit memory device, either a latch or a flip-flop. A latch is a level-sensitive memory device. A flip-flop is an edge-triggered memory device.

Foundation Express' capability to infer registers supports coding styles other than those described in this chapter. However, for best results, do the following.

• Restrict each always block to a single type of memory-element inferencing: latch, latch with asynchronous set or reset, flip-flop, flip-flop with asynchronous reset, or flip-flop with synchronous reset.
  
  
• Use the templates provided in the “Inferring Latches” section and “Inferring Flip-Flops” section of this chapter.
  
  

The Inference Report

Foundation Express generates a general inference report when building a design. It provides the asynchronous set or reset, synchronous set or reset, and synchronous toggle conditions of each latch or flip-flop, expressed in Boolean formulas. The following example shows the inference report for a JK flip-flop.

Q_reg

   Sync-reset: J' K

   Sync-set: J K'

   Sync-toggle: J K

   Sync-set and Sync-reset ==> Q: X

The inference report shows the following.

• Y indicates that the flip-flop has a synchronous reset (SR) and a synchronous set (SS).
  
  
• N indicates that the flip-flop does not have an asynchronous reset (AR), an asynchronous set (AS), or a synchronous toggle (ST).
  
  

In the inference report, the last section of the report lists the objects that control the synchronous reset and set conditions. In this example (Inference Report for a JK Flip-Flop), a synchronous reset occurs when J is low (logic 0) and K is high (logic 1). The last line of the report indicates the register output value when both the set and reset are active.

• zero (0) - Indicates that the reset has priority and the output goes to logic 0
  
  
• one (1) - Indicates that the set has priority and the output goes to logic 1
  
  
• X - Indicates that there is no priority and that the output value is unstable
  
  

The “Inferring Latches” section and “Inferring Flip-Flops” section of this chapter provide inference reports for each register template. After you read a description in Foundation Express, check the inference report.

Latch Inference Warnings

Foundation Express generates a warning message when it infers a latch. The warning message is useful to verify that a combinatorial design does not contain memory components.

Controlling Register Inference

Use directives to direct the type of sequential device you want inferred. The default is to implement the type of latch described in the HDL code. These attributes override this behavior.

The ATTRIBUTES package in the VHDL library defines the following attributes for controlling register inference.

• async_set_reset
  
  When this is set to TRUE on a signal, Foundation Express searches for a branch that uses the signal as a condition. Foundation Express then checks whether the branch contains an assignment to a constant value. If the branch does, the signal becomes an asynchronous reset or set.
  
  Attach the async_set_reset attribute to 1-bit signals using the following syntax.
  
  

  attribute async_set_reset of signal_name_list : signal is ”true”;

  
  
  
• async_set_reset_local
  
  Foundation Express treats listed signals in the specified process as if they have the async_set_reset attribute set to TRUE.
  
  Attach the async_set_reset_local attribute to a process label using the following syntax.
  
  

  attribute async_set_reset_local of process_label : label is ”signal_name_list”;

  
  
  
• async_set_reset_local_all
  
  Foundation Express treats all signals in the specified processes as if they have the async_set_reset attribute set to TRUE.
  
  Attach the async_set_reset_local_all attribute to process labels by using the following syntax.
  
  

  attribute async_set_reset_local_all of process_label_list : label is ”true”;

  
  
  
• sync_set_reset
  
  When this is set to TRUE on a signal, Foundation Express checks the signal to determine whether it synchronously sets or resets a register in the design.
  
  Attach the sync_set_reset attribute to 1-bit signals by using the following syntax.
  
  

  attribute sync_set_reset of signal_name_list :  signal is ”true”;

  
  
  
• sync_set_reset_local
  
  Foundation Express treats listed signals in the specified process as if they have the sync_set_reset attribute set to TRUE.
  
  Attach the sync_set_reset_local attribute to a process label by using the following syntax.
  
  

  attribute sync_set_reset_local of process_label : label is ”signal_name_list”;

  
  
  
• sync_set_reset_local_all
  
  Foundation Express treats all signals in the specified processes as if they have the sync_set_reset attribute set to TRUE.
  
  Attach the sync_set_reset_local_all attribute to process labels by using the following syntax.
  
  

  attribute sync_set_reset_local_all of process_label_list : label is ”true”;

  
  
  
• one_cold
  
  A one-cold implementation means that all signals in a group are active low and that only one signal can be active at a given time. The one_cold directive prevents Foundation Express from implementing priority encoding logic for the set and reset signals.
  
  Add an assertion to the VHDL code to ensure that the group of signals has a one-cold implementation. Foundation Express does not produce any logic to check this assertion.
  
  Attach the one_cold attribute to set or reset signals on sequential devices by using the following syntax.
  
  

  attribute one_cold signal_name_list : signal is ”true”;

  
  
  
• one_hot
  
  

A one_hot implementation means that all signals in a group are active-high and that only one signal can be active at a given time. The one_hot attribute prevents Foundation Express from implementing priority encoding logic for the set and reset signals.

Add an assertion to the VHDL code to ensure that the group of signals has a one_hot implementation. Foundation Express does not produce any logic to check this assertion.

Attach the one_hot attribute to set or reset signals on sequential devices using the following syntax.

attribute one_hot signal_name_list : signal is ”true”;

Inferring Latches

In simulation, a signal or variable holds its value until that output is reassigned. In hardware, a latch implements this holding-of-state capability. Foundation Express supports inference of the following types of latches.

• SR latch
  
  
• D latch
  
  
• Master-slave latch
  
  

The following sections provide details about each of these latch types.

Inferring Set/Reset (SR) Latches

Use SR latches with caution, because they are difficult to test. If you decide to use SR latches, you must verify that the inputs are hazard-free (do not glitch). During synthesis, Foundation Express does not ensure that the logic driving the inputs is hazard-free.

The following example of an SR latch provides the VHDL code that implements the SR latch described in the truth table. The inference report following the truth table for an SR latch shows the inference report that Foundation Express generates.

The following example shows an SR latch.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity sr_latch is

  port (SET, RESET : in std_logic;

        Q : out std_logic );

  attribute async_set_reset of SET, RESET :

    signal is ”true”;

end sr_latch;

architecture rtl of sr_latch is

begin

infer: process (SET, RESET) begin

  if (SET = '0') then

    Q <= '1';

  elsif (RESET = '0') then

    Q <= '0';

  end if;

end process infer;

end rtl;

The example below shows an inference report for an SR latch and its schematic.

y_reg

   Async-reset: RESET'

   Async-set: SET'

   Async-set and Async-reset ==> Q: 1

Figure 7.1 SR Latch

Inferring D Latches

When you do not specify the resulting value for an output under all conditions, as in an incompletely specified if statement, Foundation Express infers a D latch.

For example, the if statement in the following example infers a D latch because there is no else clause. The resulting value for output Q is specified only when input enable has a logic 1 value. As a result, output Q becomes a latched value.

process(DATA, GATE) begin

  if (GATE = '1') then

    Q <= DATA;

  end if;

end process;

To avoid latch inference, assign a value to the signal under all conditions, as shown in the following example.

process(DATA, GATE) begin

  if (GATE = '1') then

    Q <= DATA;

  else

    Q <= '0';

  end if;

end process;

Variables declared locally within a subprogram do not hold their value over time, because each time a subprogram is called, its variables are reinitialized. Therefore, Foundation Express does not infer latches for variables declared in subprograms. In the following example, Foundation Express does not infer a latch for output Q.

function MY_FUNC(DATA, GATE : std_logic) return                 std_logic is

     variable STATE: std_logic;

begin

  if (GATE = '1') then

    STATE <= DATA;

  end if;

  return STATE;

end;

. . .

Q <= MY_FUNC(DATA, GATE);

The following sections provide code examples, inference reports, and figures for these types of D latches.

• Simple D latch
  
  
• D latch with asynchronous set
  
  
• D latch with asynchronous reset
  
  
• D latch with asynchronous set and reset
  
  

When you infer a D latch, control the gate and data signals from the top-level design ports or through combinatorial logic. Gate and data signals that can be controlled ensure that simulation can initialize the design.

The following example provides the VHDL template for a D latch. Foundation Express generates the inference report shown after the example for a D latch. The figure “D Latch” shows the inferred latch.

library IEEE;

use IEEE.std_logic_1164.all;

entity d_latch is

  port (GATE, DATA: in std_logic;

        Q : out std_logic );

end d_latch;

architecture rtl of d_latch is

begin

infer: process (GATE, DATA) begin

  if (GATE = '1') then

    Q <= DATA;

  end if;

end process infer;

end rtl;

The example below shows an inference report for a D latch.

Q_reg

   reset/set:none

Figure 7.2 D Latch

The template in this section uses the async_set_reset attribute to direct Foundation Express to the asynchronous set (AS) pins of the inferred latch.

The following example provides the VHDL template for a D latch with an asynchronous set. Foundation Express generates the inference report shown following the example for a D latch with asynchronous set. The figure “D Latch with Asynchronous Set” shows the inferred latch.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity d_latch_async_set is

  port (GATE, DATA, SET : in std_logic;

        Q : out std_logic );

  attribute async_set_reset of SET : 

    signal is ”true”;

end d_latch_async_set;

architecture rtl of d_latch_async_set is

begin

infer: process (GATE, DATA, SET) begin

  if (SET = '0') then 

    Q <= '1';

  elsif (GATE = '1') then 

    Q <= DATA;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a D latch with asynchronous set.

Q_reg

   Async-set: SET'

Figure 7.3 D Latch with Asynchronous Set

Note: Because the target technology library does not contain a latch with an asynchronous set, Foundation Express synthesizes the set logic by using combinatorial logic.

The template in this section uses the async_set_reset attribute to direct Foundation Express to the asynchronous reset (AR) pins of the inferred latch.

The following example provides the VHDL template for a D latch with an asynchronous reset. Foundation Express generates the inference report shown following the example for a D latch with asynchronous reset. The figure “D Latch with Asynchronous Reset” shows the inferred latch.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity d_latch_async_reset is

  port (GATE, DATA, RESET : in std_logic;

        Q : out std_logic );

  attribute async_set_reset of RESET : 

    signal is ”true”;

end d_latch_async_reset;

architecture rtl of d_latch_async_reset is

begin

infer : process (GATE, DATA, RESET) begin

  if (RESET = '0') then 

    Q <= '0';

  elsif (GATE = '1') then 

    Q <= DATA;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a D latch with asynchronous reset.

Q_reg

   Async-reset: RESET'

Figure 7.4 D Latch with Asynchronous Reset

The following example provides the VHDL template for a D latch with an active-low asynchronous set and reset. This template uses the async_set_reset_local attribute to direct Foundation Express to the asynchronous signals in the infer process.

The template in the following example uses the one_cold attribute to prevent priority encoding of the set and reset signals. If you do not specify the one_cold attribute, the set signal has priority, because it is used as the condition for the if clause. Foundation Express generates the inference report shown following the example for a D latch with asynchronous set and reset. The figure “D Latch with Asynchronous Set and Reset” shows the inferred latch.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity d_latch_async is

  port (GATE, DATA, SET, RESET :in  std_logic;

        Q : out std_logic );

attribute one_cold of SET, RESET : 

    signal is ”true”;

end d_latch_async;

architecture rtl of d_latch_async is

  attribute async_set_reset_local of infer : 

    label is ”SET, RESET”;

begin

infer : process (GATE, DATA, SET, RESET) begin

  if (SET = '0') then 

    Q <= '1';

  elsif (RESET = '0') then 

    Q <= '0';

  elsif (GATE = '1') then 

    Q <= DATA;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a D latch with asynchronous set and reset.

Q_reg

   Async-reset: RESET'

   Async-set: SET'

   Async-set and Async-reset ==> Q: X

Figure 7.5 D Latch with Asynchronous Set and Reset

A variable must always have a value before it is read. As a result, a conditionally assigned variable cannot be read after the if statement in which it is assigned. A conditionally assigned variable is assigned a new value under some, but not all, conditions. The following example shows an invalid use of the conditionally assigned variable VALUE.

signal X, Y : std_logic;

. . .

process

  variable VALUE : std_logic;

begin

  if (condition) then

    VALUE <= X;

  end if;

  Y <= VALUE;  -- Invalid read of variable VALUE

end process;  

Inferring Master-Slave Latches

You can infer two-phase systems by using D latches.The following example shows a simple two-phase system with clocks MCK and SCK. The inference reports follow the example. The figure “Two-Phase Clocks” shows the inferred latch.

library IEEE;

use IEEE.std_Logic_1164.all;

entity LATCH_VHDL is

  port(MCK, SCK, DATA: in std_logic; 

       Q : out std_logic );

end LATCH_VHDL;

architecture rtl of LATCH_VHDL is

  signal TEMP : std_logic;

begin

process (MCK, DATA) begin

  if (MCK = '1') then

    TEMP <= DATA;

  end if;

end process;

process (SCK, TEMP) begin

  if (SCK = '1') then

    Q <= TEMP;

  end if;

end process;

end rtl;

TEMP_reg

   reset/set: none

Q_reg

  reset/set: none

Figure 7.6 Two-Phase Clocks

Inferring Flip-Flops

Foundation Express can infer D flip-flops, JK flip-flops, and toggle flip-flops. The following sections provide details about each of these flip-flop types.

Many FPGA devices have a dedicated set/reset hardware resource that should be used. For this reason, you should infer asynchronous set/reset signals for all flip-flops in the design. Foundation Express will then use the global set/reset lines.

Inferring D Flip-Flops

Foundation Express infers a D flip-flop whenever the condition of a wait or if statement uses an edge expression (a test for the rising or falling edge of a signal). Use the following syntax to describe a rising edge.

SIGNAL'event and SIGNAL = '1'

Use the following syntax to describe a falling edge.

SIGNAL'event and SIGNAL = '0'

If you are using the IEEE std_logic_1164 package, you can use the following syntax to describe a rising edge and a falling edge.

if (rising_edge (CLK)) then

if (falling_edge (CLK)) then

If you are using the IEEE std_logic_1164 package, you can use the following syntax for a bused clock. You can also use a member of a bus as a signal.

sig (3)'event and sig (3) = '1'

rising_edge (sig(3))

A wait statement containing an edge expression causes Foundation Express to create flip-flops for all signals, and some variables are assigned values in the process. The following example shows the most common usage of the wait statement to infer a flip-flop.

process

begin

  wait until (edge); 

  ...

end process;

An if statement implies flip-flops for signals and variables in the branches of the if statement. The following example shows the most common usages of the if statement to infer a flip-flop.

process (sensitivity_list)

begin

  if (edge) 

    ...

  end if;

end process;

process (sensitivity_list)

begin

  if (...) then

    ...

  elsif (...)

    ...

  elsif (edge) then

    ...

  end if;

end process;

You can sometimes use wait and if statements interchangeably. If possible, use the if statement, because it provides greater control over the inferred registers.

The following sections provide code examples, inference reports, and figures for these types of D flip-flops.

• Positive edge-triggered D flip-flop
  
  
• Positive edge-triggered D flip-flop using rising_edge
  
  
• Negative edge-triggered D flip-flop
  
  
• Negative edge-triggered D flip-flop using falling_edge
  
  
• D flip-flop with asynchronous set
  
  
• D flip-flop with asynchronous reset
  
  
• D flip-flop with asynchronous set and reset
  
  
• D flip-flop with synchronous set
  
  
• D flip-flop with synchronous reset
  
  
• D flip-flop with synchronous and asynchronous load
  
  
• Multiple flip-flops with asynchronous and synchronous controls
  
  

When you infer a D flip-flop, control the clock and data signals from the top-level design ports or through combinatorial logic. Clock and data signals that can be controlled ensure that simulation can initialize the design. If you cannot control the clock and data signals, infer a D flip-flop with asynchronous reset or set or with a synchronous reset or set.

The following example provides the VHDL template for a positive edge-triggered D flip-flop. Foundation Express generates the inference report shown following the example for a positive edge-triggered D flip-flop. The figure “Positive-Edge-Triggered D Flip-flop” shows the inferred flip-flop.

library IEEE ;

use IEEE.std_logic_1164.all;

entity dff_pos is

  port (DATA, CLK : in std_logic;

        Q : out std_logic );

end dff_pos;

architecture rtl of dff_pos is

begin

infer : process (CLK) begin

  if (CLK'event and CLK = '1') then 

    Q <= DATA;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a positive edge-triggered D flip-flop.

Q_reg

   set/reset/toggle: none

Figure 7.7 Positive Edge-Triggered D Flip-Flop

The following example provides the VHDL template for a positive edge-triggered D flip-flop using the IEEE_std_logic_1164 package and rising_edge.

Foundation Express generates the inference report shown after the example. The figure following the inference report shows the inferred flip-flop.

library IEEE ;

use IEEE.std_logic_1164.all;

entity dff_pos is

  port (DATA, CLK : in std_logic;

        Q : out std_logic );

end dff_pos;

architecture rtl of dff_pos is

begin

infer : process (CLK) begin

  if (rising_edge (CLK)) then 

    Q <= DATA;

  end if;

end process infer;

end rtl;

Q_reg

   set/reset/toggle: none

Figure 7.8 Positive Edge-Triggered D Flip-Flop Using rising_edge

The following example provides the VHDL template for a negative edge-triggered D flip-flop. Foundation Express generates the inference report following the example for a negative edge-triggered D flip-flop. The figure “Negative Edge-Triggered D Flip-Flop” shows the inferred flip-flop.

library IEEE;

use IEEE.std_logic_1164.all;

entity dff_neg is

  port (DATA, CLK : in std_logic;

        Q : out std_logic );

end dff_neg;

architecture rtl of dff_neg is

begin

infer : process (CLK) begin

  if (CLK'event and CLK = '0') then 

    Q <= DATA;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a negative edge-triggered D flip-flop.

Q_reg

   set/reset/toggle: none

Figure 7.9 Negative Edge-Triggered D Flip-Flop

The following example provides the VHDL template for a negative edge-triggered D flip-flop using the IEEE_std_logic_1164 package and falling_edge.

Foundation Express generates the inference report shown after the following example. The figure following the inference report shows the inferred flip-flop.

library IEEE;

use IEEE.std_logic_1164.all;

entity dff_neg is

  port (DATA, CLK : in std_logic;

        Q : out std_logic );

end dff_neg;

architecture rtl of dff_neg is

begin

infer : process (CLK) begin

  if (falling_edge (CLK)) then 

    Q <= DATA;

  end if;

end process infer;

end rtl;

Q_reg

   set/reset/toggle: none

Figure 7.10 Negative Edge-Triggered D Flip-Flop Using falling_edge

The following example provides the VHDL template for a D flip-flop with an asynchronous set. Foundation Express generates the inference report shown following the example for a D flip-flop with asynchronous set. The figure “D Flip-Flop with Asynchronous Set” shows the inferred flip-flop.

library IEEE;

use IEEE.std_logic_1164.all;

entity dff_async_set is

  port (DATA, CLK, SET : in std_logic;

        Q : out std_logic );

end dff_async_set;

architecture rtl of dff_async_set is

begin

infer : process (CLK, SET) begin

  if (SET = '0') then 

    Q <= '1';

  elsif (CLK'event and CLK = '1') then 

    Q <= DATA;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a D flip-flop with asynchronous set.

Q_reg

   Async-set: SET'

Figure 7.11 D Flip-Flop with Asynchronous Set

The following example provides the VHDL template for a D flip-flop with an asynchronous reset. Foundation Express generates the inference report following the example for a D flip-flop with asynchronous reset. The figure “D Flip-Flop with Asynchronous Reset” shows the inferred flip-flop.

library IEEE;

use IEEE.std_logic_1164.all;

entity dff_async_reset is

  port (DATA, CLK, RESET : in std_logic;

        Q : out std_logic );

end dff_async_reset;

architecture rtl of dff_async_reset is

begin

infer : process ( CLK, RESET) begin

  if (RESET = '1') then 

    Q <= '0';

  elsif (CLK'event and CLK = '1') then 

    Q <= DATA;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a D flip-flop with asynchronous reset.

Q_reg

   Async-reset: RESET

Figure 7.12 D Flip-Flop with Asynchronous Reset

The following example provides the VHDL template for a D flip-flop with active high asynchronous set and reset pins. The template uses the one_hot attribute to prevent priority encoding of the set and reset signals. If you do not specify the one_hot attribute, the reset signal has priority, because it is used as the condition for the if clause. Foundation Express generates the inference report following the example for a D flip-flop with asynchronous set and reset. The figure “D Flip-Flop with Asynchronous Set and Reset” shows the inferred flip-flop.

Note: Most FPGA architectures do not have a register with an asynchronous set and asynchronous reset cell available. For this reason, avoid this construct.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity dff_async is

  port (DATA, CLK, SET, RESET : in std_logic;

        Q : out std_logic );

  attribute one_hot of SET, RESET : signal is ”true”;

end dff_async;

architecture rtl of dff_async is

begin

infer : process (CLK, SET, RESET) begin

  if (RESET = '1') then 

    Q <= '0';

  elsif (SET = '1') then

    Q <= '1';

  elsif (CLK'event and CLK = '1') then

    Q <= DATA;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a D flip-flop with asynchronous set and reset.

Q_reg

   Async-reset: RESET

   Async-set: SET

   Async-set and Async-reset ==> Q: X

Figure 7.13 D Flip-flop with Asynchronous Set and Reset

The previous examples illustrate how to infer a D flip-flop with asynchronous controls - one way to initialize or control the state of a sequential device. You can also synchronously reset or set the flip-flop (see the following two examples in the next section). The sync_set_reset attribute directs Foundation Express to the synchronous controls of the sequential device.

When the target technology library does not have a D flip-flop with synchronous reset, Foundation Express infers a D flip-flop with synchronous reset logic as the input to the D pin of the flip-flop. If the reset (or set) logic is not directly in front of the D pin of the flip-flop, initialization problems can occur during gate-level simulation of the design.

The following example provides the VHDL template for a D flip-flop with synchronous set. Foundation Express generates the inference report shown following the example for a D flip-flop with synchronous set. The figure “D Flip-Flop with Synchronous Set” shows the inferred flip-flop.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity dff_sync_set is

  port (DATA, CLK, SET : in std_logic;

        Q : out std_logic );

  attribute sync_set_reset of SET : signal is ”true”;

end dff_sync_set;

architecture rtl of dff_sync_set is

begin

infer : process (CLK) begin

  if (CLK'event and CLK = '1') then 

    if (SET = '1') then 

      Q <= '1';

    else 

      Q <= DATA;

    end if;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a D flip-flop with synchronous set.

Q_reg

   Sync-set: SET

Figure 7.14 D Flip-Flop with Synchronous Set

The following example provides the VHDL template for a D flip-flop with synchronous reset. Foundation Express generates the inference report shown following the example for a D flip-flop with synchronous reset. The figure “D Flip-Flop with Synchronous Reset” shows the inferred flip-flop.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity dff_sync_reset is

  port (DATA, CLK, RESET : in std_logic;

        Q : out std_logic );

attribute sync_set_reset of RESET : 

    signal is ”true”;

end dff_sync_reset;

architecture rtl of dff_sync_reset is

begin

infer : process (CLK) begin

  if (CLK'event and CLK = '1') then 

    if (RESET = '0') then 

      Q <= '0';

    else 

      Q <= DATA;

    end if;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a D flip-flop with synchronous reset.

Q_reg

   Sync-reset: RESET'

Figure 7.15 D Flip-Flop with Synchronous Reset

D flip-flops can have asynchronous or synchronous controls. You must check the asynchronous conditions before you check the synchronous conditions.

The following example provides the VHDL template for a D flip-flop with synchronous load (called SLOAD) and an asynchronous load (called ALOAD). Foundation Express generates the inference report shown following the example for a D flip-flop with synchronous and asynchronous load. The figure “D Flip-Flop with Synchronous and Asynchronous Load” shows the inferred flip-flop.

library IEEE;

use IEEE.std_logic_1164.all;

entity dff_a_s_load is

  port(SLOAD, ALOAD, ADATA, SDATA, 

       CLK : in std_logic;

       Q : out std_logic );

end dff_a_s_load;

architecture rtl of dff_a_s_load is

begin

infer: process (CLK, ALOAD) begin

  if (ALOAD = '1') then 

    Q <= ADATA;

  elsif (CLK'event and CLK = '1') then 

    if (SLOAD = '1') then 

      Q <= SDATA;

    end if;

  end if;

end process infer;

end rtl;

The following example shows an inference report for a D flip-flop with synchronous and asynchronous load.

Q_reg

   set/reset/toggle: none

Figure 7.16 D Flip-Flop with Synchronous and Asynchronous Load

If a signal is synchronous in one process but asynchronous in another, use the sync_set_reset_local and async_set_reset_local attributes to direct Foundation Express to the correct implementation.

In the following example, block infer_sync uses the reset signal as a synchronous reset, and the process infer_async uses the reset signal as an asynchronous reset. Foundation Express generates the inference report shown following the example for multiple flip-flops with asynchronous and synchronous controls. The figure “Multiple Flip-flops with Asynchronous and Synchronous Controls” shows the resulting design.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity multi_attr is

  port (DATA1, DATA2, CLK, RESET, SLOAD : in               std_logic;

        Q1, Q2 : out std_logic );

end multi_attr; 

architecture rtl of multi_attr is

  attribute async_set_reset_local of infer_async : 

    label is ”RESET”;

  attribute sync_set_reset_local of infer_sync : 

    label is ”RESET”;

begin

infer_sync: process (CLK) begin

  if (CLK'event and CLK = '1') then

    if (RESET = '0') then

      Q1 <= '0';

    elsif (SLOAD = '1') then

      Q1 <= DATA1;

    end if;

  end if;

end process infer_sync;

infer_async: process (CLK, RESET) begin

  if (RESET = '0') then

    Q2 <= '0';

  elsif (CLK'event and CLK = '1') then

    if (SLOAD = '1') then

      Q2 <= DATA2;

    end if;

  end if;

end process infer_async;

end rtl;

The following example shows inference reports for multiple flip-flops with asynchronous and synchronous controls.

Q1_reg

   Sync-reset: RESET'

Q2_reg

   Async-reset: RESET'

Figure 7.17 Multiple Flip-Flops with Asynchronous and Synchronous Controls

A flip-flop inference has specific limitations. See the “Understanding Limitations of Register Inference” section of this chapter.

Inferring JK Flip-Flops

When you infer a JK flip-flop, make sure you can control the J, K, and clock signals from the top-level design ports to ensure that simulation can initialize the design.The following sections provide code examples, inference reports, and figures for these types of JK flip-flops.

• JK flip-flop
  
  
• JK flip-flop with asynchronous set and reset
  
  

When you infer a JK flip-flop, make sure you can control the J, K, and clock signals from the top-level design ports to ensure that simulation can initialize the design.

In the JK flip-flop, the J and K signals act as active-high synchronous set and reset. Use the sync_set_reset directive to indicate that the J and K signals are the synchronous set and reset for the design.

Table 7_1 Truth Table for JK Flip-Flop

The following example provides the VHDL code that implements the JK flip-flop described in the truth table.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity jk is

  port(J, K, CLK : in std_logic; 

       Q_out : out std_logic );

  attribute sync_set_reset of J, K : 

    signal is ”true”;

end jk;

architecture rtl of jk is

  signal Q : std_logic;

begin

infer: process 

  variable JK : std_logic_vector ( 1 downto 0);

begin

  wait until (CLK'event and CLK = '1');

  JK <= (J & K);

  case JK is

    when ”01” => Q <= '0';

    when ”10” => Q <= '1';

    when ”11” => Q <= not (Q);

    when ”00” => Q <= Q;

    when others => Q <= 'X';

  end case;

end process infer;

Q_out <= Q;

end rtl;

The following example shows the inference report generated by Foundation Express for a JK flip-flop, and the figure following the report, “JK Flip-Flop,” shows the inferred flip-flop.

Q_reg

   Sync-reset: J' K

   Sync-set: J K'

   Sync-toggle: J K

   Sync-set and Sync-reset ==> Q: X

Figure 7.18 JK Flip-Flop

Use the sync_set_reset attribute to indicate the JK function. Use the one_hot attribute to prevent priority encoding of the J and K signals.

The following example provides the VHDL template for a JK flip-flop with asynchronous set and reset.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity jk_async_sr is

  port (SET, RESET, J, K, CLK : in std_logic;

        Q_out : out std_logic );

  attribute sync_set_reset of J, K : 

    signal is ”true”;

  attribute one_hot of SET,RESET : signal is ”true”;

end jk_async_sr;

architecture rtl of jk_async_sr is

  signal Q : std_logic;

begin

infer : process (CLK, SET, RESET) 

  variable JK : std_logic_vector (1 downto 0);

begin

  if (RESET = '1') then 

    Q <= '0';

  elsif (SET = '1') then 

    Q <= '1';

  elsif (CLK'event and CLK = '1') then 

    JK <= (J & K);

    case JK is

      when ”01” => Q <= '0';

      when ”10” => Q <= '1';

      when ”11” => Q <= not(Q);

      when ”00” => Q <= Q;

      when others => Q <= 'X';

    end case;

  end if;

end process infer;

Q_out <= Q;

end rtl;

The following table shows the inference report Foundation Express generates for a JK flip-flop with asynchronous set and reset, and the figure following the report, “JK Flip-Flop with Asynchronous Set and Reset,” shows the inferred flip-flop.

Q_reg

    Async-reset: RESET

    Async-set: SET

    Sync-reset: J' K

    Sync-set: J K'

    Sync-toggle: J K

    Async-set and Async-reset ==> Q: X

    Sync-set and Sync-reset ==> Q: X

Figure 7.19 JK Flip-Flop with Asynchronous Set and Reset

Inferring Toggle Flip-Flops

To infer toggle flip-flops, follow the coding style in the following examples. You must include asynchronous controls in the toggle flip-flop description. Without them, you cannot initialize toggle flip-flops to a known state.

The following sections provide code examples, inference reports, and figures for these types of toggle flip-flops.

• Toggle flip-flop with asynchronous set
  
  
• Toggle flip-flop with asynchronous reset
  
  
• Toggle flip-flop with enable and asynchronous reset
  
  

The following example shows the VHDL template for a toggle flip-flop with asynchronous set. Foundation Express generates the inference report shown following the example, and the figure “Toggle Flip-Flop with Asynchronous Set” shows the flip-flop.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

entity t_async_set is

  port(SET, CLK : in std_logic;

       Q : out std_logic );

end t_async_set;

architecture rtl of t_async_set is

  signal TMP_Q : std_logic;

begin

infer: process (CLK, SET) begin

  if (SET = '1') then 

    TMP_Q <= '1';

  elsif (CLK'event and CLK = '1') then 

    TMP_Q <= not (TMP_Q);

  end if;  

  Q <= TMP_Q;

end process infer;

end rtl;

TMP_Q_reg

   Async-set: SET

   Sync-toggle: true

Figure 7.20 Toggle Flip-Flop with Asynchronous Set

The following example provides the VHDL template for a toggle flip-flop with asynchronous reset. The table following the example shows the inference report, and the figure following the report, “Toggle Flip-Flop with Asynchronous Reset,” shows the inferred flip-flop.

library IEEE ;

use IEEE.std_logic_1164.all;

entity t_async_reset is

  port(RESET, CLK : in std_logic;

       Q : out std_logic );

end t_async_reset;

architecture rtl of t_async_reset is

  signal TMP_Q : std_logic;

begin

infer: process (CLK, RESET) begin

  if (RESET = '1') then 

    TMP_Q <= '0';

  elsif (CLK'event and CLK = '1') then 

    TMP_Q <= not (TMP_Q);

  end if;  

  Q <= TMP_Q;

end process infer;

end rtl;

TMP_Q_reg

    Async-reset: RESET

    Sync-toggle: true

Figure 7.21 Toggle Flip-Flop with Asynchronous Reset

The following example provides the VHDL template for a toggle flip-flop with an enable and an asynchronous reset. The flip-flop toggles only when the enable (TOGGLE signal) has a logic 1 value.

Foundation Express generates the inference report shown following the example, and the figure following the report, “Toggle Flip-Flop with Enable and Asynchronous Reset,” shows the inferred flip-flop.

library IEEE, synopsys;

use IEEE.std_logic_1164.all;

use synopsys.attributes.all;

entity t_async_en_r is

  port(RESET, TOGGLE, CLK : in std_logic; 

       Q : out std_logic );

end t_async_en_r;

architecture rtl of t_async_en_r is

  signal TMP_Q : std_logic;

begin

infer: process (CLK, RESET) begin

  if (RESET = '1') then 

    TMP_Q <= '0';

  elsif (CLK'event and CLK = '1') then 

    if (TOGGLE = '1') then 

      TMP_Q <= not (TMP_Q);

    end if;

  end if;  

end process infer;

Q <= TMP_Q;

end rtl;

TMP_Q_reg

   Async-reset: RESET

   Sync-toggle: TOGGLE

Figure 7.22 Toggle Flip-Flop with Enable and Asynchronous Reset

Getting the Best Results

This section provides tips for improving the results you achieve during flip-flop inference. The following topics are covered.

• Minimizing flip-flop count
  
  
• Correlating synthesis results with simulation results
  
  

HDL descriptions should build only as many flip-flops as the design requires.

The following example shows a description that infers too many flip-flops. The inference report is shown following the example. The figure “Circuit with Six Inferred Flip-Flops” shows the inferred flip-flops.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity count is

  port (CLK, RESET : in std_logic;

        AND_BITS, OR_BITS, 

        XOR_BITS : out std_logic );

end count;

architecture rtl of count is

begin

process

  variable COUNT : std_logic_vector (2 downto 0);

begin

  wait until (CLK'event and CLK = '1');

  if (RESET = '1') then

    COUNT <= ”000”;

  else 

    COUNT <= COUNT + 1;

  end if;

  AND_BITS <= COUNT(2) and COUNT(1) and COUNT(0);

  OR_BITS <= COUNT(2) or COUNT(1) or COUNT(0);

  XOR_BITS <= COUNT(2) xor COUNT(1) xor COUNT(0);

end process;

end rtl;

The following example has only one process, which contains a wait statement and six output signals. Foundation Express infers six flip-flops, one for each output signal in the process.

• COUNT(2:0) (three inferred flip-flops)
  
  
• AND_BITS (one inferred flip-flop)
  
  
• OR_BITS (one inferred flip-flop)
  
  
• XOR_BITS (one inferred flip-flop)
  
  

However, because the outputs AND_BITS, OR_BITS, and XOR_BITS depend solely on the value of variable COUNT, and variable COUNT is registered, these three outputs do not need to be registered. Therefore, assign AND_BITS, OR_BITS, and XOR_BITS within a process that does not have a wait statement (see the next section, “Circuit Description Inferring Correct Number of Flip-Flops”).

Figure 7.23 Circuit with Six Inferred Flip-Flops

To avoid inferring extra flip-flops, assign the output signals from within a process that does not have a wait statement.

The following example shows a description with two processes, one with a wait statement and one without. The registered (synchronous) assignments are in the first process, which contains the wait statement. The other (asynchronous) assignments are in the second process. Signals communicate between the two processes.

This description style lets you choose the signals that are registered and those that are not. The inference report is shown following the example. The figure “Circuit with Three Inferred Flip-Flops” shows the resulting circuit.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity count is

  port(CLK, RESET : in std_logic; 

       AND_BITS, OR_BITS, XOR_BITS : out std_logic);

end count;

architecture rtl of count is

  signal COUNT : std_logic_vector (2 downto 0);

begin

reg : process begin

  wait until (CLK'event and CLK = '1');

  if (RESET = '1') then

    COUNT <= ”000”;

  else

    COUNT <= COUNT + 1;

  end if;

end process reg;

combine : process(count) begin

  AND_BITS <= COUNT(2) and COUNT(1) and COUNT(0);

  OR_BITS <= COUNT(2) or COUNT(1) or COUNT(0);

  XOR_BITS <= COUNT(2) xor COUNT(1) xor COUNT(0);

end process combine;

end rtl;

COUNT_reg (width 3)

   set/reset/toggle: none

Figure 7.24 Circuit with Three Inferred Flip-Flops

This technique of separating combinatorial logic from registered or sequential logic in your design is useful when describing finite state machines. See these in the “Examples” appendix.

• “Moore Machine”
  
  
• “Mealy Machine”
  
  
• “Count Zeros - Sequential Version””
  
  
• “Soft Drink Machine - State Machine Version”
  
  

Using delay specifications with registered values can cause the simulation to behave differently from the logic Foundation Express synthesizes. For example, the description in the following example contains delay information that causes Foundation Express to synthesize a circuit that behaves unexpectedly (the post-synthesis simulation results do not match the pre-synthesis simulation results).

component flip_flop (D, CLK : in std_logic;

                     Q : out std_logic );

end component;

process (A, CLK);

  signal B: std_logic;

begin

  B <= A after 100ns;

  F1: flip_flop port map (A, CLK, C),

  F2: flip_flop port map (B, CLK, D);

end process;

In the above example, B changes 100 nanoseconds after A changes. If the clock period is less than 100 nanoseconds, output D is one or more clock cycles behind output C during simulation of the design. However, because Foundation Express ignores the delay information, A and B change values at the same time and so do C and D. This behavior is not the same as in the post-synthesis simulation.

When using delay information in your designs, make sure that the delays do not affect registered values. In general, you can safely include delay information in your description if it does not change the value that gets clocked into a flip-flop.

Understanding Limitations of Register Inference

Foundation Express cannot infer the following components. You must instantiate these components in your VHDL description.

• Flip-flops and latches with three-state outputs
  
  
• Flip-flops with bidirectional pins
  
  
• Flip-flips with multiple clock inputs
  
  
• Multiport latches
  
  
• Register banks
  
  

  Note: Although you can instantiate flip-flops with bidirectional pins, Foundation Express interprets these cells as black boxes.

If you use an if statement to infer D flip-flops, your design must meet the following requirements.

• An edge expression must be the only condition of an if or an elsif clause.
  
  The following if statement is invalid because it has multiple conditions in the if clause.
  
  

  if (edge and RST = '1') 

  
  
  
• You can have only one edge expression in an if clause, and the if clause must not have an else clause.
  
  The following if statement is invalid, because you cannot include an else clause when using an edge expression as the if or elsif condition.
  
  

  if X > 5 then
  
    sequential_statement;
  
  elsif edge then
  
    sequential_statement;
  
  else
  
    sequential_statement;
  
  end if;

  
  
  
• An edge expression cannot be part of another logical expression or be used as an argument.
  
  The following function call is invalid, because you cannot use the edge expression as an argument.
  
  

  any_function(edge);