Istype
Attributes for CPLD Designs - Overview
| Attribute | Description | Xilinx Support |
| 'buffer' | Non-inverted signal | Directly Supported |
| 'collapse' | Collapse (remove) this signal | Directly Supported |
| 'com' | Combinatorial signal | Directly Supported |
| 'dc' | Unspecified logic is don't care | Directly Supported |
| 'invert' | Inverted signal | Emulated |
| 'keep' | Do not collapse this signal from equations | Directly Supported |
| 'neg' | Unspecified logic is 1 | Directly Supported |
| 'pos' | Unspecified logic is 0 | Directly Supported |
| 'reg' | Registered output signal | Directly Supported |
| 'reg_D' | Registered output signal for D Flip-flop | Directly Supported |
| 'reg_G' | Registered gated clock memory element | Emulated |
| 'reg_JK' | JK-type registered output signal | Emulated |
| 'reg_SR' | SR-type registered output signal | Emulated |
| 'reg_T' | T-type registered output signal | Directly Supported |
| 'retain'
|
Do not minimize output. Preserve redundant product terms | Directly Supported |
| 'xor' | XOR gate | Directly Supported |