Xilinx Design Flow

The “Xilinx Design Flow” figure shows the processing steps and flow of files in and out of the Design Manager. The “Detailed Design Flow” figure is a more detailed look at the various programs invoked during the design implementation process.

Figure 4.1 Xilinx Design Flow

Figure 4.2 Detailed Design Flow

Using the Design Manager

NOTE

Refer to the Design Manager/Flow Engine Reference User Guide for detailed information on using the Design Manager.

Figure 4.3 Design Manager Menu

Creating a Project

Use the following steps to create a new project in the Design Manager.

1. Select File New Project from the Design Manager menu or click the New Project toolbar button. The New Project dialog box appears.
   
   
2. Specify a design file to open with one of the following methods.
   
   
   • In the Input Design field, type the name of a design file to open.
     
     
   • Click the Input Design Browse button to the right of the Input Design box to select the top level input netlist. Click OK.
     
     

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     NOTE

     The Design Manager automatically creates a subdirectory named xproj under the input design directory and uses it as the work directory. The Design Manager uses the xproj subdirectory to store all the data files for the project. If you want to change this default work directory, type a path in the Work Directory field or use Browse to select a directory.

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3. In the New Project dialog box, click OK.
   
   After your design is loaded, the Design Manager window appears, configured for the loaded design.
   
   

For information on using the Xilinx-supplied interface tools for Synopsys, Viewlogic, Mentor Graphics, or Cadence designs, see the following appropriate appendix.

• “Cadence Concept and Verilog Interface Notes” appendix
  
  
• “Alliance FPGA Express Interface Notes” appendix
  
  
• “Mentor Graphics Interface Notes” appendix
  
  
• “Synopsys (XSI) Interface Notes” appendix
  
  
• “Viewlogic Interface Notes” appendix
  
  
• “Instantiated Components” appendix
  
  

Implementing Your Design

1. Select Design Implement from the Design Manager menu or click the Implement toolbar button. The Implement dialog box appears.
   
   
2. Select the part and click on Run. The Design Manager automatically creates a new version and revision. Additional versions are created when the netlist is modified and re-implemented. Additional revisions are created when the same netlist is re-implemented with new options or constraints. The Design Manager invokes the Flow Engine to process your design.
   
   

Using the Flow Engine

The Flow Engine allows you to process and control the implementation of your design, as well as guide your implementation revisions. The following figure shows the various steps followed by the Flow Engine to process your designs.

Figure 4.4 Flow Engine Design Steps

Translating Your Design

The Flow Engine's first step, Translate, merges all of the input netlists by running the NGDBuild program.

Mapping Your Design

Mapping your design is the next step in the design flow. Map optimizes the gates and trims unused logic in the merged NGD netlist. Map also maps your design's logic resources and performs a physical design rule check.

Placing and Routing Your Design

After mapping, the Flow Engine places and routes your design. The PAR (Place and Route) program is invoked to optimally place and route the mapped CLBs and IOBs in your design. If there are timing constraints on any of the logic components, PAR attempts to minimize those delays by moving the corresponding logic blocks closer together. In the route stage, the logic blocks are assigned specific interconnect elements on the die. PAR attempts to minimize any delays by selecting a faster interconnect.

Configuring Your Design

After placing and routing your design, the Flow Engine translates the physical implementation into a binary stream that is used to program an FPGA.This binary stream is saved as a configuration file (.bit) using the BitGen program.

Analyzing Reports with the Design Manager

Design Manager reports provide information on logic trimming, logic optimization, timing constraint performance, and I/O pin assignment. To access the reports, select the following from the Design Manager menu.

Utilities Report Browser

To open a specific report, double click on its icon, as shown in the following figure.

Figure 4.5 Report Browser

Translation Report

The Translation Report contains warning and error messages from the three translation processes: conversion of the EDIF or XNF style netlist to the Xilinx NGD netlist; timing specification checks; and logical design rule checks. The report lists the following.

• Hierarchical blocks that are missing or cannot be translated
  
  
• Invalid or incomplete timing constraints
  
  
• Output contention, loadless outputs, and sourceless inputs
  
  

Map Report

The Map Report (.mrp file) contains warning and error messages detailing logic optimization and logic mapping to physical resources. The report lists the following information.

• Removed Logic - Sourceless and loadless signals can cause the removal of an entire chain of logic. Each deleted element is listed with progressive indentation so you can easily identify the origins of the removed logic sections; deletion statements are not indented.
  
  
• Added or expanded logic due to speed optimization.
  
  
• The Design Summary lists the number and percentage of used CLBs, IOBs, flip-flops, and latches. It also lists the use of architecture-specific resources such as global buffers and boundary scan logic.
  
  

Place and Route Report

The Place and Route Report (.par file) contains the following information.

• Design Score - The Design Score measures the relative goodness of your design; a lower score is better. Because this score is strongly dependent on the nature of your design and the targeted part, meaningful score comparisons can only be made between iterations of the same design targeted for the same part.
  
  
• The Number of Signals Not Completely Routed should be zero for a completely implemented design. If not, you may be able to improve results by using the re-entrant route flow or the multi-pass place and route flow. See the “Advanced Implementation Flows” section at the end of this chapter.
  
  
• The timing summary at the end of the report contains the timing performance of your design. For information on timing constraint performance and synchronous delays, refer to the “Static Timing Analysis” section later in this chapter.
  
  

Pad Report

The Pad Report lists your design's pinout sorted by signal name, and then by pin number.