Chapter 3

Design Entry

This chapter describes Cadence design entry in relation to the Xilinx Development software. This chapter does not discuss in detail how to use the Concept design tools. This chapter describes design entry procedures only for Xilinx-specific software, libraries, and features.

For a detailed description of the Concept design entry tools and procedures, refer to the Concept Schematic User Guide. For a list of the manuals that describe the Synergy tool, see the “Verilog HDL Design Entry” section in this chapter.

Before using the design entry tools, ensure that you have set up your environment as described in the “Required Software” section of the “Getting Started” chapter.

This chapter contains the following sections.

• “Concept”
  
  
• “Requirements For HDL Direct Compliance”
  
  
• “Using the Xilinx Concept Unified Schematic Libraries”
  
  
• “Renamed Components”
  
  
• “Verilog/Concept HDL Direct Naming Conventions”
  
  
• “VCC and GND Components”
  
  
• “Using the LogiBLOX Libraries”
  
  
• “Specifying Xilinx Properties and Constraints in Concept”
  
  
• “Attaching Signal Names”
  
  
• “Creating Bus Taps”
  
  
• “Using the BSCAN Symbol”
  
  
• “Using the STARTUP Symbol”
  
  
• “Using the CONFIG Symbol to Specify Part Type”
  
  
• “Using HDL Direct Methodology”
  
  
• “Creating Bodies for Non-Schematic Design Blocks”
  
  
• “Verilog HDL Design Entry”
  
  
• “Translating Your Design”