Chapter 4

Using the Floorplanner

This chapter provides step-by-step instructions for performing the important floorplanning tasks.

These procedures are presented in sequential order; however, not every task that can be performed is documented in this chapter. Floorplanning a design may require you to repeat some procedures several times. Consult the design flows in the “Design Flow” chapter to aid your floorplanning efforts.

For information on starting and exiting the Floorplanner, see the “Getting Started” chapter.

This chapter contains the following sections.

• “Opening a File” describes how to load a design file into the Floorplanner.
  
  
• “Saving a File” explains how to save your floorplanned design.
  
  
• “Using Colors” explains how to assign different colors to the hierarchical groups display.
  
  
• “Floorplanning Logic” describes how to move logic symbols from the Design Hierarchy window to the Floorplan window.
  
  
• “Floorplanning Designs that Contain RPMs” explains how to floorplan designs that contain Relationally Placed Macros (RPMs).
  
  
• “Creating Groups” explains how to rearrange and regroup the design hierarchy.
  
  
• “Using Area Constraints” describes how to create area constraints.
  
  
• “Flattening and Building the Hierarchy” describes how to flatten and rebuild the design hierarchy.
  
  
• “Walking Through the Design” describes how to select successive logic by connectivity rather than by name.
  
  
• “Analyzing PAR Placement” describes how to analyze the placement results that PAR generates.
  
  
• “Analyzing PAR Placement for Timing Constraints” describes how to analyze the placement of floorplanned logic by PAR with respect to Timing Constraints.
  
  
• “Finding Logic Connected to Nets” explains how to find logic that is connected to nets in the floorplanned design.
  
  
• “Displaying Resources and Logic” describes how to display the logic resources that are available on the FPGA.
  
  
• “Performing Detailed Manual Placement” explains how to manually place logic into the Floorplanner window.
  
  
• “Checking the Floorplan” describes how to check the floorplanned logic for placement problems.
  
  
• “Aligning Symbols” describes how to align symbols in the Floorplan window to reduce unnecessary routing.
  
  
• “Working with Patterns” describes how to work with patterns when you place selected logic in the Floorplan window.
  
  
• “How to Interleave Buses” describes how to interleave buses in the Floorplan design.
  
  
• “Iterative Floorplanning” explains how to floorplan your design iteratively.
  
  
• “Floorplanning Incremental Schematic Changes” describes how to make incremental changes to a design that has been previously implemented in an FPGA.
  
  
• “Making Small Modifications to Automatic Placement” describes how to make small changes to an automatically placed design in order to fix packing or placement problems.
  
  
• “Lock Down I/Os from Automatically Placed Design” describes how to select the I/Os from an automatically placed and routed design and lock them down in the Floorplan window.
  
  
• “Getting Started With an Unfamiliar Design” describes how to familiarize yourself with the connectivity of someone else's design.