CPLD Design Techniques

The following topics provide useful information and design techniques that show the most efficient ways of implementing your CPLD designs.

Design Creation	Design Optimization
Bidirectional Signals	Global Nets - Clocks, 3-State, Set/Reset
Counters	Local Feedback (XC9500) - for Extra Speed
Latches	Logic Optimization - Speed vs Density
Multiplexing vs 3-State Buses	Pin Assignment - Manual Control
Read-Back Registers	Pin Locking
	Power Consumption - for Macrocells
	Register Initial States - for Power Up
	Slew Rate - for Output Pins
	Timing Constraints - for Speed Critical Paths
	Using Clock Enable